VHDL-AMS based genetic optimisation of fuzzy logic controllers

Purpose – This paper presents a VHDL-AMS based genetic optimisation methodology for fuzzy logic controllers (FLCs) used in complex automotive systems and modelled in mixed physical domains. A case study applying this novel method to an active suspension system has been investigated to obtain a new type of fuzzy logic membership function with irregular shapes optimised for best performance. Design/methodology/approach – The geometrical shapes of the fuzzy logic membership functions are irregular and optimised using a genetic algorithm (GA). In this optimisation technique, VHDL-AMS is used not only for the modelling and simulation of the FLC and its underlying active suspension system but also for the implementation of a parallel GA directly in the system testbench. Findings – Simulation results show that the proposed FLC has superior performance in all test cases to that of existing FLCs that use regular-shape, triangular or trapezoidal membership functions. Research limitations – The test of the FLC has only been done in the simulation stage, no physical prototype has been made. Originality/value – This paper proposes a novel way of improving the FLC’s performance and a new application area for VHDL-AMS

VHDL-AMS based genetic optimization of a fuzzy logic controller for automotive active suspension systems

This paper presents a new type of fuzzy logic controller (FLC) membership functions for automotive active suspension systems. The shapes of the membership functions are irregular and optimized using a genetic algorithm (GA). In this optimization technique, VHDL-AMS is used not only for the modeling and simulation of the fuzzy logic controller and its underlying active suspension system but also for the implementation of a parallel GA. Simulation results show that the proposed FLC has superior performance to that of existing FLCs that use triangular or trapezoidal membership functions

Behavioral simulation and synthesis of biological neuron systems using synthesizable VHDL

Neurons are complex biological entities which form the basis of nervous systems. Insight can be gained into neuron behavior through the use of computer models and as a result many such models have been developed. However, there exists a trade-off between biological accuracy and simulation time with the most realistic results requiring extensive computation. To address this issue, a novel approach is described in this paper that allows complex models of real biological systems to be simulated at a speed greater than real time and with excellent accuracy. The approach is based on a specially developed neuron model VHDL library which allows complex neuron systems to be implemented on field programmable gate array (FPGA) hardware. The locomotion system of the nematode Caenorhabditis elegans is used as a case study and the measured results show that the real time FPGA based implementation performs 288 times faster than traditional ModelSim simulations for the same accuracy

Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed

Determining DfT Hardware by VHDL-AMS Fault Simulation for Biological Micro-Electronic Fluidic Arrays

The interest of microelectronic fluidic arrays for biomedical applications, like DNA determination, is rapidly increasing. In order to evaluate these systems in terms of required Design-for-Test structures, fault simulations in both fluidic and electronic domains are necessary. VHDL-AMS can be used successfully in this case. This paper shows a highly testable architecture of a DNA Bio-Sensing array, its basic sensing concept, fluidic modeling and sensitivity analysis. The overall VHDL-AMS fault simulation of the system is shown

AER-based robotic closed-loop control system

Address-Event-Representation (AER) is an asynchronous protocol for transferring the information of spiking neuro-inspired systems. Actually AER systems are able to see, to ear, to process information, and to learn. Regarding to the actuation step, the AER has been used for implementing Central Pattern Generator algorithms, but not for controlling the actuators in a closed-loop spike-based way. In this paper we analyze an AER based model for a real-time neuro-inspired closed-loop control system. We demonstrate it into a differential control system for a two-wheel vehicle using feedback AER information. PFM modulation has been used to power the DC motors of the vehicle and translation into AER of encoder information is also presented for the close-loop. A codesign platform (called AER-Robot), based into a Xilinx Spartan 3 FPGA and an 8051 USB microcontroller, with power stages for four DC motors has been used for the demonstrator.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-0

AER and dynamic systems co-simulation over Simulink with Xilinx System Generator

Address-Event Representation (AER) is a neuromorphic communication protocol for transferring information of spiking neurons implemented into VLSI chips. These neuro-inspired implementations have been used to design sensor chips (retina, cochleas), processing chips (convolutions, filters) and learning chips, what makes possible the development of complex, multilayer, multichip neuromorphic systems. In biology one of the last steps of the processing is to move a muscle, to apply the results of these complex neuromorphic processing to the real world. One interesting question is to be able to transform, or translate, the AER information into robot movements, like for example, moving a DC motor. This paper presents several ways to translate AER spikes into DC motor power, and to control a DC motor speed, based on Pulse Frequency Modulation. These methods have been simulated into Simulink with Xilinx System Generator, and tested into the AER-Robot platform.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-0

Using an FPGA for Fast Bit Accurate SoC Simulation

In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit completely on the simulation platform (i.e. FPGA). As a case study, we use a Network-on-Chip (NoC) that is simulated in SystemC and on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a factor 80-300 of speed improvement, without compromising the cycle and bit level accuracy

VSS : a VHDL synthesis system

This report describes a register transfer synthesis system that allows a designer to interact with the design process. The designer can modify the compiled design by changing the input description, selecting optimization and mapping strategies, or graphically changing the generated design schematic. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization. The compilation process consists of two phases. First, a design composed of generic components is synthesized from the input description. Second, this design is translated into components from a particular library by a mapper and optimized by a logic optimizer. Redesign to new technologies can be accomplished by changing only the component library