Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling

It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successful test generation approaches to reduce IR-drop and/or power supply noise during LTC for the launch-off capture (LOC) scheme have previously been proposed, and several of X-filling techniques have proven especially effective. With X-filling in the launch-off shift (LOS) scheme, however, adjacent-fill (which was originally proposed for shift-in power reduction) is used frequently. In this work, we propose a novel X-filling technique for the LOS scheme, called Adjacent-Probability-based X-Filling (AP-fill), which can reduce more LTC power than adjacent-fill. We incorporate AP-fill into a post-ATPG test modification flow consisting of test relaxation and X-filling in order to avoid the fault coverage loss and the test vector count inflation. Experimental results for larger ITC\u2799 circuits show that the proposed AP-fill technique can achieve a higher power reduction ratio than 0-fill, 1-fill, and adjacent-fill.2011 Asian Test Symposium, 20-23 November 2011, New Delhi, Indi

Low-Cost On-Chip Clock Jitter Measurement Scheme

In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Improving the performance of Virtualized Network Services based on NFV and SDN

Network Functions Virtualisation (NFV) proposes to move all the traditional network appliances, which require dedicated physical machine, onto virtualised environment (e.g,. Virtual Machine). In this way, many of the current physical devices present in the infrastructure are replaced with standard high volume servers, which could be located in Datacenters, at the edge of the network and in the end user premises. This enables a reduction of the required physical resources thanks to the use of virtualization technologies, already used in cloud computing, and allows services to be more dynamic and scalable. However, differently from traditional cloud applications which are rather demanding in terms of CPU power, network applications are mostly I/O bound, hence the virtualization technologies in use (either standard VM-based or lightweight ones) need to be improved to maximize the network performance. A series of Virtual Network Functions (VNFs) can be connected to each other thanks to Software-Defined Networks (SDN) technologies (e.g., OpenFlow) to create a Network Function Forwarding Graph (NF-FG) that processes the network traffic in the configured order of the graph. Using NF-FGs it is possible to create arbitrary chains of services, and transparently configure different virtualized network services, which can be dynamically instantiated and rearranges depending on the requested service and its requirements. However, the above virtualized technologies are rather demanding in terms of hardware resources (mainly CPU and memory), which may have a non-negligible impact on the cost of providing the services according to this paradigm. This thesis will investigate this problem, proposing a set of solutions that enable the novel NFV paradigm to be efficiently used, hence being able to guarantee both flexibility and efficiency in future network services

유전알고리즘 및 강화학습을 사용한 고속 회로 설계 자동화 프레임워크

학위논문(석사) -- 서울대학교대학원 : 융합과학기술대학원 지능정보융합학과, 2022.2. 전동석.Although design automation is a key enabler of modern large-scale digital systems, automating the transistor-level circuit design process still remains a challenge. Some recent works suggest that deep learning algorithms could be adopted to find optimal transistor dimensions in relatively small circuitry such as analog amplifiers. However, those approaches are not capable of exploring different circuit structures to meet the given design constraints. In this work, we propose an automatic circuit design framework that can generate practical circuit structures from scratch as well as optimize the size of each transistor, considering performance and reliability. We employ the framework to design level shifter circuits, and the experimental results show that the framework produces novel level shifter circuit topologies and the automatically optimized designs achieve 2.8-5.3× lower PDP than prior arts designed by human experts.설계 자동화는 대규모 디지털 시스템을 가능하게 하는 핵심 요소이지만 트랜지스터 수준에서 회로 설계 프로세스를 자동화하는 것은 여전히 어려운 과제로 남아 있습니다. 최근 연구에서는 아날로그 앰프와 같은 비교적 작은 회로에서 최적의 성능을 보이는 트랜지스터 크기를 찾기 위해 deep learning 알고리즘을 활용할 수 있다고 말합니다. 그러나 이러한 접근 방식은 주어진 설계 constraint를 충족하는 다른 회로 구조 탐색에 적용하기 어렵습니다. 본 연구에서는 성능과 신뢰성을 고려하여 각 트랜지스터의 크기를 최적화할 뿐만 아니라 처음부터 실용적인 회로 구조를 생성할 수 있는 자동 회로 설계 framework를 제안합니다. 우리는 framework를 사용하여 level shifter 회로를 설계했으며 실험 결과는 프레임워크가 새로운 level shifter 회로 토폴로지를 생성하고 자동으로 최적화된 설계가 인간 전문가가 설계한 선행 기술보다 2.8-5.3배 더 낮은 PDP를 달성한다는 것을 보여줍니다.Abstract i Contents ii List of Tables iv List of Figures v List of Algorithms vi 1 Introduction 1 2 Related work 6 2.1 Genetic Algorithm 6 2.2 NeuroEvolution of Augmenting Topologies (NEAT) 7 2.3 Reinforcement Learning (RL) 10 2.4 DDPG, D4PG, and PPO 12 2.5 Level Shifter 14 3 Proposed circuit design framework 17 3.1 Topology Generator 17 3.2 Circuit Optimizer 25 4 Experiment Result 32 4.1 Level Shifter Design 32 4.2 Topology Generation 34 4.3 Circuit Optimization 36 4.4 Test Chip Fabrication 42 4.5 Applicability of Topology Generator 47 5 Conclusion 50 Abstract (In Korean) 57석

ARTIFICIAL INTELLIGENT REMOTE CONTROL CAR (AI MOBILE) (A.K.A. REMOTE CONTROL CAR USING MATLAB)

The primary objective of this project is to construct a working prototype of a remote controlled car (a.k.a. AI Mobile) and its ability to control from MATLAB Graphical User Interface (GUI). It involves several EE areas in microcontroller, wireless communication and MATLAB. Secondary objective will be implementing artificial intelligence (AI) in a robot to perform tasks intelligently and autonomously. The car will be enhanced with systems like obstacles detection sensors, wireless camera, wireless microphone, and speed alteration. These systems will be combined by the PIC microcontroller and controlled from the remote computer with the aid of the MS Visual Basic GUI. With these artificial intelligent systems, successful execution of manyhuman-in-loop manipulation tasks which directlydepend on the operator's skill previously can be improved to: (i) permit easy and rapid incorporation of local sensory information to augment performance, and (ii) provide variable performance (precision- and power-) assist for output motions and forces. Such AI systems have enormous potential both reduce operator error and permit integration of greater autonomy into human and robot interactions which will eventually enhance security, safety, and performance. The AI systems are built on an existing platform modified from a remote controlled car. The processor used to coordinate the AI Mobile is the microcontroller PIC16F84A. The independent subsystems for controlling the AI Mobile via Microsoft Visual Basic include the serial communication interface, switching circuit, microcontroller, RF Transmitter & Receiver and Visual Basic programming