33 research outputs found

    Synthèse de réseaux de distribution d'horloges en présence de variations du procédé de fabrication

    Get PDF
    Design of clock distributions networks in presence of process variations -- Importance des variations spatiales de la constante de temps du transistor MOS -- Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations -- Conception de réseaux de distribution d'horloges fiables et à faible consommation de puissance -- Design of low-power and reliable logic-based H-trees -- Sources des variations spatiales de la constante de temps du transistor MOS -- Spatial characterization of process variations via MOS transistor time constants in VLSI & WSI -- Techniques de minimisation du biais de synchronisation par calibration de délai -- Minimizing process-induced skew using delay tuning

    Development of Si/SiGe technology for microwave integrated circuits

    Get PDF
    A complete fabrication process has been developed for the realisation of Si/SiGe microwave integrated circuits (SIMICs). Using the process, a number of active and passive elements for microwave circuits have been demonstrated including 1. Metal gate p-SiGe MOSFETs . 2. Low loss transmission lines on CMOS grade silicon. 3. High quality spiral inductors on CMOS grade silicon. 4. High performance metal gate strained silicon n-MOSFETs. Single stage amplifiers have been designed based on the technology developed in this work. The MOSFETs have good DC performance. Strained SiGe p-channel MOSFETs with 1 mum gate length have an extrinsic transconductance of 36 mS/mm. Strained silicon n-channel MOSFETs with 0.3 mum gate length have extrinsic transconductance of 230 mS/mm. The RF performance of a metal gate 0.3 mum gate length strained silicon MOSFET is measured, with cut off frequency and maximum frequency of oscillation of 20 GHz and 21 GHz respectively. Coplanar waveguide transmission lines of 50 Ohm characteristic impedance, fabricated using spin on dielectrics on a CMOS grade silicon subsfrate, have losses less than 0.5 dB/mm up to 60 GHz. Spiral inductors fabricated on the low loss dielectric have Q > 15. Using the passive and active element library developed, single stage amplifiers were designed with gain of 12 dB at 3 GHz or 7.5 dB at 6 GHz. The device layer structures were designed using a simple ID Poisson solver. The p-channel device used a concentration graded SiGe channel to obtain high mobility and carrier concentration. The n-channel RF device with a strained silicon channel incorporates a metal gate technology that is'directly responsible for the high values of f achieved. The spiral inductors and coplanar waveguides are fabricated using a spin on dielectric process to separate them from the lossy silicon substrate. The same technology is used to reduce the parasitic capacitance of device contact pads. The engineering conclusion of this work is that SIMICs, for applications in the frequency range 1 to 10 GHz, can be made with the current passive and active element library at the University of Glasgow. Further improvement in both passive and active element performance to increase the frequency is set out in future work. From a practical viewpoint a process is now in place that will underpin the University of Glasgow's Si / SiGe SIMIC projects in the future

    Solid State Circuits Technologies

    Get PDF
    The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

    Advanced Platform Systems Technology study. Volume 2: Trade study and technology selection

    Get PDF
    Three primary tasks were identified which include task 1-trade studies, task 2-trade study comparison and technology selection, and task 3-technology definition. Task 1 general objectives were to identify candidate technology trade areas, determine which areas have the highest potential payoff, define specific trades within the high payoff areas, and perform the trade studies. In order to satisfy these objectives, a structured, organized approach was employed. Candidate technology areas and specific trades were screened using consistent selection criteria and considering possible interrelationships. A data base comprising both manned and unmanned space platform documentation was used as a source of system and subsystem requirements. When requirements were not stated in the data base documentation, assumptions were made and recorded where necessary to characterize a particular spacecraft system. The requirements and assumptions were used together with the selection criteria to establish technology advancement goals and select trade studies. While both manned and unmanned platform data were used, the study was focused on the concept of an early manned space station

    Local Epitaxial Overgrowth for Stacked Complementary MOS Transistor Pairs

    Get PDF
    A three-dimensional silicon processing technology for CMOS circuits was developed and characterized. The first fully depleted SOI devices with individually biasable gates on both sides of the silicon film were realized. A vertically stacked CMOS Inverter built by lateral overgrowth was reported for the first time. Nucleation-free epitaxial lateral overgrowth of silicon over thin oxides was developed for both a pancake and a barrel-type epitaxy reactor: This process was optimized to limit damage to gate oxides and minimize dopant diffusion within the Substrate. Autodoping from impurities of the MOS transistors built in the substrate was greatly reduced. A planarisation technique was developed to reduce the silicon film thickness from 13μm to below 0.5μm for full depletion. Chemo-mechanical polishing was modified to yield an automatic etch stop with the corresponding control and uniformity of the silicon film. The resulting wafer topography is more planar than in a conventional substrate CMOS process. PMOS transistors which match the current drive of bulk NM0S devices of equal geometry were characterized, despite the three-times lower hole mobility. Devices realized in the substrate, at the bottom and on top of the SOI film were essentially indistinguishable from bulk devices. A novel device with two insulated gates controlling the same channel was characterized. Inverters were realized both as joint-gate configuration and with symmetric performance of n- and p-channel. These circuits were realized in the area of a single NMOS transistor

    Crosstalk computing: circuit techniques, implementation and potential applications

    Get PDF
    Title from PDF of title [age viewed January 32, 2022Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (page 117-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2020This work presents a radically new computing concept for digital Integrated Circuits (ICs), called Crosstalk Computing. The conventional CMOS scaling trend is facing device scaling limitations and interconnect bottleneck. The other primary concern of miniaturization of ICs is the signal-integrity issue due to Crosstalk, which is the unwanted interference of signals between neighboring metal lines. The Crosstalk is becoming inexorable with advancing technology nodes. Traditional computing circuits always tries to reduce this Crosstalk by applying various circuit and layout techniques. In contrast, this research develops novel circuit techniques that can leverage this detrimental effect and convert it astutely to a useful feature. The Crosstalk is engineered into a logic computation principle by leveraging deterministic signal interference for innovative circuit implementation. This research work presents a comprehensive circuit framework for Crosstalk Computing and derives all the key circuit elements that can enable this computing model. Along with regular digital logic circuits, it also presents a novel Polymorphic circuit approach unique to Crosstalk Computing. In Polymorphic circuits, the functionality of a circuit can be altered using a control variable. Owing to the multi-functional embodiment in polymorphic-circuits, they find many useful applications such as reconfigurable system design, resource sharing, hardware security, and fault-tolerant circuit design, etc. This dissertation shows a comprehensive list of polymorphic logic gate implementations, which were not reported previously in any other work. It also performs a comparison study between Crosstalk polymorphic circuits and existing polymorphic approaches, which are either inefficient due to custom non-linear circuit styles or propose exotic devices. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to Crosstalk Computing, which leads to benefits in the circuit density, power, and performance. The circuit simulation and characterization results show a 6x improvement in transistor count, 2x improvement in switching energy, and 1.5x improvement in performance compared to counterpart implementation in CMOS circuit style. Nevertheless, the Crosstalk circuits also face issues while cascading the circuits; this research analyzes all the problems and develops auxiliary circuit techniques to fix the problems. Moreover, it shows a module-level cascaded polymorphic circuit example, which also employs the auxiliary circuit techniques developed. For the very first time, it implements a proof-of-concept prototype Chip for Crosstalk Computing at TSMC 65nm technology and demonstrates experimental evidence for runtime reconfiguration of the polymorphic circuit. The dissertation also explores the application potentials for Crosstalk Computing circuits. Finally, the future work section discusses the Electronic Design Automation (EDA) challenges and proposes an appropriate design flow; besides, it also discusses ideas for the efficient implementation of Crosstalk Computing structures. Thus, further research and development to realize efficient Crosstalk Computing structures can leverage the comprehensive circuit framework developed in this research and offer transformative benefits for the semiconductor industry.Introduction and Motivation -- More Moore and Relevant Beyond CMOS Research Directions -- Crosstalk Computing -- Crosstalk Circuits Based on Perception Model -- Crosstalk Circuit Types -- Cascading Circuit Issues and Sollutions -- Existing Polymorphic Circuit Approaches -- Crosstalk Polymorphic Circuits -- Comparison and Benchmarking of Crosstalk Gates -- Practical Realization of Crosstalk Gates -- Poential Applications -- Conclusion and Future Wor

    Chemical Vapor Deposition of Copper Films.

    Get PDF
    We have studied the kinetics of copper chemical vapor deposition (CVD) for interconnect metallization using hydrogen (H\sb2) reduction of the Cu(hfac)\sb2 (copper(II) hexafluoroacetylacetonate) precursor. Steady-state deposition rates were measured using a hot-wall microbalance reactor. For base case conditions of 2 Torr Cu(hfac)\sb2, 40 Torr H\sb2, and 300\sp\circC, a growth rate of 0.5 mg cm\sp{-2} hr\sp{-1} (ca. 10 nm min\sp{-1}) is observed. Reaction order experiments suggest that the deposition rate passes through a maximum at partial pressure of 2 Torr of Cu(hfac)\sb2. The deposition rate has an overall half-order dependence on H\sb2 partial pressure. A Langmuir-Hinshelwood rate expression is used to describe the observed kinetic dependencies on Cu(hfac)\sb2, H\sb2, and H(hfac). Based on the rate expression a mechanism is proposed in which the overall rate is determined by the surface reaction of adsorbed Cu(hfac)\sb2 and H species. Additionally, the role of alcohols in enhancing the deposition rate has been investigated. Addition of isopropanol results in a six fold enhancement to yield a deposition rate of 3.3 mg cm\sp{-2} hr\sp{-1} (ca. 60 nm min\sp{-1}) at 5 Torr of isopropanol, 0.4 Torr Cu(hfac)\sb2, 40 Torr H\sb2, and 300\sp\circC. Ethanol and methanol give lower enhancements of 1.75 and 1.1 mg cm\sp{-2} hr\sp{-1}, respectively. A mechanism based on the ordering of the aqueous pK\sb{\rm a} values of the alcohols is proposed to explain the observed results. Lastly, we have built a warm-wall Pedestal reactor apparatus to demonstrate copper CVD on TiN/Si substrates. The apparatus includes a liquid injection system for transport of isopropanol-diluted precursor solutions. At optimized conditions of precursor and substrate pre-treatments, we have deposited uniform films of copper on TiN/Si substrates at an average deposition rate of 3.0 mg cm\sp{-2} hr\sp{-1} (ca. 60 nm min\sp{-1})

    Advanced Platform Systems Technology study. Volume 3: Supporting data

    Get PDF
    The overall study effort proceeded from the identification of 106 technology topics to the selection of 5 for detail trade studies. The technical issues and options were evaluated through the trade process. Finally, individual consideration was given to costs and benefits for the technologies identified for advancement. Eight priority technology items were identified for advancement. Supporting data generated during the trade selection and trade study process were presented. Space platform requirements, trade study and cost benefits analysis, and technology advancement planning are advanced. The structured approach used took advantage of a number of forms developed to ensure that a consistent approach was employed by each of the diverse specialists that participated. These forms were an intrinsic part of the study protocol

    College of Engineering

    Full text link
    Cornell University Courses of Study Vol. 91 1999/200

    College of Engineering

    Full text link
    Cornell University Courses of Study Vol. 91 1999/200
    corecore