Spice model of current polarity-dependent piecewise linear window function for memristors

Memristor and memristive systems are nonlinear systems. It is important to model them accurately. There are different memristor models and most of the models make use of window functions. In literature, there are various window functions. Recently, a piecewise linear (PWL) window function is used to model a memristor and memristive systems. Such a memristor with a PWL window function lacks a SPICE model. Also, in literature, there is current polarity dependent window functions proposed for memristors to model polarity dependent drift speed within the thin-film memristors. In this study, an alternative current-polarity dependent PWL window function is suggested to model a memristor, a different PWL function one for each current polarity is used, its SPICE model is made in LTSpice and also its simulation results are given. Such a model can be used to model the polarity dependent drift speed within the thin-film memristors. © 2020, Gazi Universitesi. All rights reserved

The Fourth Element: Characteristics, Modelling, and Electromagnetic Theory of the Memristor

In 2008, researchers at HP Labs published a paper in {\it Nature} reporting the realisation of a new basic circuit element that completes the missing link between charge and flux-linkage, which was postulated by Leon Chua in 1971. The HP memristor is based on a nanometer scale TiO$_2$ thin-film, containing a doped region and an undoped region. Further to proposed applications of memristors in artificial biological systems and nonvolatile RAM (NVRAM), they also enable reconfigurable nanoelectronics. Moreover, memristors provide new paradigms in application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). A significant reduction in area with an unprecedented memory capacity and device density are the potential advantages of memristors for Integrated Circuits (ICs). This work reviews the memristor and provides mathematical and SPICE models for memristors. Insight into the memristor device is given via recalling the quasi-static expansion of Maxwell's equations. We also review Chua's arguments based on electromagnetic theory.Comment: 28 pages, 14 figures, Accepted as a regular paper - the Proceedings of Royal Society

Modeling the Flux-Charge Relation of Memristor with Neural Network of Smooth Hinge Functions

The memristor was proposed to characterize the flux-charge relation. We propose the generalized flux-charge relation model of memristor with neural network of smooth hinge functions. There is effective identification algorithm for the neural network of smooth hinge functions. The representation capability of this model is theoretically guaranteed. Any functional flux-charge relation of a memristor can be approximated by the model. We also give application examples to show that the given model can approximate the flux-charge relation of existing piecewise linear memristor model, window function memristor model, and a physical memristor device

Everything You Wish to Know About Memristors But Are Afraid to Ask

This paper classifies all memristors into three classes called Ideal, Generic, or Extended memristors. A subclass of Generic memristors is related to Ideal memristors via a one-to-one mathematical transformation, and is hence called Ideal Generic memristors. The concept of non-volatile memories is defined and clarified with illustrations. Several fundamental new concepts, including Continuum-memory memristor, POP (acronym for Power-Off Plot), DC V-I Plot, and Quasi DC V-I Plot, are rigorously defined and clarified with colorful illustrations. Among many colorful pictures the shoelace DC V-I Plot stands out as both stunning and illustrative. Even more impressive is that this bizarre shoelace plot has an exact analytical representation via 2 explicit functions of the state variable, derived by a novel parametric approach invented by the author

Device Modeling and Circuit Design of Neuromorphic Memory Structures

The downscaling of CMOS technology and the benefits gleaned thereof have made it the cornerstone of the semiconductor industry for many years. As the technology reaches its fundamental physical limits, however, CMOS is expected to run out of steam instigating the exploration of new nanoelectronic devices. Memristors have emerged as promising candidates for future computing paradigms, specifically, memory arrays and neuromorphic circuits. Towards this end, this dissertation will explore the use of two memristive devices, namely, Transition Metal Oxide (TMO) devices and Insulator Metal Transition (IMT) devices in constructing neuromorphic circuits. A compact model for TMO devices is first proposed and verified against experimental data. The proposed model, unlike most of the other models present in the literature, leverages the instantaneous resistance of the device as the state variable which facilitates parameter extraction. In addition, a model for the forming voltage of TMO devices is developed and verified against experimental data and Monte Carlo simulations. Impact of the device geometry and material characteristics of the TMO device on the forming voltage is investigated and techniques for reducing the forming voltage are proposed. The use of TMOs in syanptic arrays is then explored and a multi-driver write scheme is proposed that improves their performance. The proposed technique enhances voltage delivery across the selected cells via suppressing the effective line resistance and leakage current paths, thus, improving the performance of the crossbar array. An IMT compact model is also developed and verified against experiemntal data and electro-thermal device simulations. The proposed model describes the device as a memristive system with the temperature being the state variable, thus, capturing the temperature dependent resistive switching of the IMT device in a compact form suitable for SPICE implementation. An IMT based Integrate-And-Fire neuron is then proposed. The IMT neuron leverages the temperature dynamics of the device to deliver the functionality of the neuron. The proposed IMT neuron is more compact than its CMOS counterparts as it alleviates the need for complex CMOS circuitry. Impact of the IMT device parameters on the neuron\u27s performance is then studied and design considerations are provided

An Investigation into Neuromorphic ICs using Memristor-CMOS Hybrid Circuits

The memristance of a memristor depends on the amount of charge flowing through it and when current stops flowing through it, it remembers the state. Thus, memristors are extremely suited for implementation of memory units. Memristors find great application in neuromorphic circuits as it is possible to couple memory and processing, compared to traditional Von-Neumann digital architectures where memory and processing are separate. Neural networks have a layered structure where information passes from one layer to another and each of these layers have the possibility of a high degree of parallelism. CMOS-Memristor based neural network accelerators provide a method of speeding up neural networks by making use of this parallelism and analog computation. In this project we have conducted an initial investigation into the current state of the art implementation of memristor based programming circuits. Various memristor programming circuits and basic neuromorphic circuits have been simulated. The next phase of our project revolved around designing basic building blocks which can be used to design neural networks. A memristor bridge based synaptic weighting block, a operational transconductor based summing block were initially designed. We then designed activation function blocks which are used to introduce controlled non-linearity. Blocks for a basic rectified linear unit and a novel implementation for tan-hyperbolic function have been proposed. An artificial neural network has been designed using these blocks to validate and test their performance. We have also used these fundamental blocks to design basic layers of Convolutional Neural Networks. Convolutional Neural Networks are heavily used in image processing applications. The core convolutional block has been designed and it has been used as an image processing kernel to test its performance.Comment: Bachelor's thesi

Reliable SPICE Simulations of Memristors, Memcapacitors and Meminductors

Memory circuit elements, namely memristive, memcapacitive and meminductive systems, are gaining considerable attention due to their ubiquity and use in diverse areas of science and technology. Their modeling within the most widely used environment, SPICE, is thus critical to make substantial progress in the design and analysis of complex circuits. Here, we present a collection of models of different memory circuit elements and provide a methodology for their accurate and reliable modeling in the SPICE environment. We also provide codes of these models written in the most popular SPICE versions (PSpice, LTspice, HSPICE) for the benefit of the reader. We expect this to be of great value to the growing community of scientists interested in the wide range of applications of memory circuit elements

SPICE compact modeling of bipolar/unipolar memristor switching governed by electrical thresholds

In this work we propose a physical memristor/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship. The proposed model is capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time.The developed compact model has been validated against two physical devices, fitting unipolar and bipolar switching. With no requirement of Verilog-A code, LTSpice and Spectre simulations reproduce distinctive phenomena such as the preforming state, voltage/cycle dependent<br/

Spatiotemporal Pattern Detection with Neuromorphic Circuits

In this dissertation, neuromorphic circuits are used to implement spiking neural networks in order to detect spatiotemporal patterns. Unsupervised training and detection-by-design techniques were used to attain the appropriate connectomes and perform pattern detection. Unsupervised training was performed by feeding random digital spikes with a repeating embedded spatiotemporal pattern to a spiking neural network composed of leaky integrate-and-fire neurons and memristor-R(t) element circuits which implement spike-timing-dependent plasticity learning rules. Detection-by-design was achieved using neuromporphic circuits and digital logic gates. When detection-by-design was achieved using both neuromorphic circuits and digital logic gates, a network was created of spatiotemporal pattern detector circuits, each of which was capable of detecting the three fundamental spatiotemporal patterns (NA-NA-Δt, NA-NB-Δt, and NA-NB-Coincidence), in order to detect combinations of two-spike features in the desired spatiotemporal pattern. The spatiotemporal pattern was detected when all of the two-spike features were detected. Similarly, when detection-by-design was achieved using only neuromorphic circuits, a Complex Pattern Detecting Network was was formed by combining Simple Pattern Detecting Networks, each of which was capable of detecting the three fundamental spatiotemporal patterns. The Complex Pattern Detector was used in a proof-of-concept to demonstrate a detect-and-generate spatiotemporal symbol computing paradigm