Accelerated Frame Data Relocation on Xilinx Field Programmable Gate Array

Emerging reconfiguration techniques that include partial dynamic reconfiguration and partial bitstream relocation have been addressed in the past in order to expose the flexibility of field programmable gate array at runtime. Partial bitstream relocation is a technique used to target a partial bitstream of a partial reconfigurable region (PRR) onto other identical reconfigurable regions inside an FPGA, while partial dynamic reconfiguration is used to target a single reconfigurable region. Prior works in this domain aim to minimize relocation time with the help of on-chip or on-line processing. In this thesis, a novel PRR-PRR relocation algorithm is proposed and implemented both in software and hardware. Dedicated hardware architecture, called the accelerated relocation circuit (ARC), is designed and presented for fast relocation. An analytical model is also proposed to evaluate the performance of the PRR-PRR relocation algorithm and highlight the speed-up obtained by the proposed hardware implementation. ARC has been tested on two categories of designs: dynamically scalable systolic array designs and fault tolerant designs. It has been compared against the software implementation of the algorithm, BiRF, hardware architecture for bitstream relocation, and a software solution for bitstream relocation. An average speed-up of 153x for ARC over BiRF is observed, with the additional advantage of not storing any bitstreams, thus saving invaluable block random access memory (BRAMs). Accuracy of proposed analytical model was found to be more than 95% for all the test cases

FPGA dynamic and partial reconfiguration : a survey of architectures, methods, and applications

Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows, and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption

Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

Modern FPGAs with run-time reconfiguration allow the implementation of complex systems offering both the flexibility of software-based solutions combined with the performance of hardware. This combination of characteristics, together with the development of new specific methodologies, make feasible to reach new points of the system design space, and make embedded systems built on these platforms acquire more and more importance. However, the practical exploitation of this technique in fields that traditionally have relied on resource restricted embedded systems, is mainly limited by strict power consumption requirements, the cost and the high dependence of DPR techniques with the specific features of the device technology underneath. In this work, we tackle the previously reported problems, designing a reconfigurable platform based on the low-cost and low-power consuming Spartan-6 FPGA family. The full process to develop the platform will be detailed in the paper from scratch. In addition, the implementation of the reconfiguration mechanism, including two profiles, is reported. The first profile is a low-area and low-speed reconfiguration engine based mainly on software functions running on the embedded processor, while the other one is a hardware version of the same engine, implemented in the FPGA logic. This reconfiguration hardware block has been originally designed to the Virtex-5 family, and its porting process will be also described in this work, facing the interoperability problem among different families

The distinct distribution of two Dictyostelium Talins

Although the distinct distribution of certain molecules along the anterior or posterior edge is essential for directed cell migration, the mechanisms to maintain asymmetric protein localization have not yet been fully elucidated. Here, we studied a mechanism for the distinct localizations of two Dictyostelium talin homologues, talin A and talin B, both of which play important roles in cell migration and adhesion. Using GFP fusion, we found that talin B, as well as its C-terminal actin-binding region, which consists of an I/LWEQ domain and a villin headpiece domain, was restricted to the leading edge of migrating cells. This is in sharp contrast to talin A and its C-terminal actin-binding domain, which co-localized with myosin II along the cell posterior cortex, as reported previously. Intriguingly, even in myosin II-null cells, talin A and its actin-binding domain displayed a specific distribution, co-localizing with stretched actin filaments. In contrast, talin B was excluded from regions rich in stretched actin filaments, although a certain amount of its actin-binding region alone was present in those areas. When cells were sucked by a micro-pipette, talin B was not detected in the retracting aspirated lobe where acto-myosin, talin A, and the actin-binding regions of talin A and talin B accumulated. Based on these results, we suggest that talin A predominantly interacts with actin filaments stretched by myosin II through its C-terminal actin-binding region, while the actin-binding region of talin B does not make such distinctions. Furthermore, talin B appears to have an additional, unidentified mechanism that excludes it from the region rich in stretched actin filaments. We propose that these actin-binding properties play important roles in the anterior and posterior enrichment of talin B and talin A, respectively, during directed cell migration

Design abstraction for autonomous adaptive hardware systems on FPGAs

Adaptive hardware is gaining importance with the emergence of more autonomous systems that must process large volumes of sensor data and react within tight deadlines. To support such computation within the constraints of embedded deployments, a blend of high throughput hardware processing and adaptive control is required. FPGAs offer an ideal platform for implementing such systems by virtue of their hardware flexibility and sensor interfacing capabilities. FPGA SoCs are specifically well suited offering capable embedded processors that are tightly coupled with a flexible high performance FPGA fabric. This paper explores existing work on adaptive hardware systems before proposing a general model and implementation approach tailored towards these modern FPGA architectures, concluding with pointers for research in this emerging field

Embedded electronic systems driven by run-time reconfigurable hardware

Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria

From MARTE to dynamically reconfigurable FPGAs : Introduction of a control extension in a model based design flow

System-on-Chip (SoC) can be considered as a particular case of embedded systems and has rapidly became a de-facto solution for implement- ing these complex systems. However, due to the continuous exponential rise in SoC's design complexity, there is a critical need to find new seamless method- ologies and tools to handle the SoC co-design aspects. This paper addresses this issue and proposes a novel SoC co-design methodology based on Model Driven Engineering (MDE) and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by OMG (Object Management Group), in order to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs; and allow to implement the notion of Partial Dy- namic Reconfiguration supported by current FPGAs. The overall objective is to carry out system modeling at a high abstraction level expressed in UML (Unified Modeling Language); and afterwards, transform these high level mod- els into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis

Scientific Achievements and legacy of Professor Eduardo Couve Montané: A narrative review.

Reviewing the history and achievements of professors can teach and inspire the next generation to pursue their research and legacy. For this reason, the present paper reviews the scientific achievements and legacy of Professor Eduardo Couve.Professor Eduardo Couve developed an outstanding academic career in the University of Valparaíso. In his research he merged his knowledge in cell and oral biology with his accurate management of microscopy, especially electron and confocal microscopes. This allowed him to develop interesting and diverse papers.Through all his research it is possible to observe a logical and consistent cycle of evidence production influenced by advances in microscopy and collaborations. The conceptualization of the pulp as a sensory organ and a multicellular barrier from an evolutionary perspective, shows a thorough analysis and reflective process of the available evidence and the influence of the different areas of knowledge for a better understanding of dental pulp and tooth.The real impact of his influence on the countless generations he taught and on all the colleagues he worked with and enjoyed collaborations with, may never be measured, but surely the influence of his career and research will be present for a long time in the development of dental research both in Chile and abroad.Reviewing the history and achievements of professors can teach and inspire the next generation to pursue their research and legacy. For this reason, the present paper reviews the scientific achievements and legacy of Professor Eduardo Couve. Professor Eduardo Couve developed an outstanding academic career in the University of Valparaíso. In his research he merged his knowledge in cell and oral biology with his accurate management of microscopy, especially electron and confocal microscopes. This allowed him to develop interesting and diverse papers. Through all his research it is possible to observe a logical and consistent cycle of evidence production influenced by advances in microscopy and collaborations. The conceptualization of the pulp as a sensory organ and a multicellular barrier from an evolutionary perspective, shows a thorough analysis and reflective process of the available evidence and the influence of the different areas of knowledge for a better understanding of dental pulp and tooth. The real impact of his influence on the countless generations he taught and on all the colleagues he worked with and enjoyed collaborations with, may never be measured, but surely the influence of his career and research will be present for a long time in the development of dental research both in Chile and abroad

Contextual effects of immigrant presence on populist radical right support: testing the ‘halo effect’ on Front National voting in France

This paper examines the relationship between immigration and populist radical right (PRR) support, based on an analysis of the contextual effects of immigrant presence on Front National vote in France in 2017. Using a unique set of survey data geolocalising respondents at the subcommunal level, it finds evidence for the existence of a curvilinear “halo effect,” with substantial increases in the probability of PRR vote in areas surrounding communities with significantly higher-than-average immigrant populations, and independent of other socio-economic context, as well as individual socio-demographic characteristics. Most importantly, a path analysis confirms the presence of individual attitudinal mediators of this halo effect on PRR vote, thus testing the foundation of the halo, namely that the contextual effects of immigrant presence act on attitudes which drive PRR support. These findings provide a significant step forward in understanding the mechanisms linking subjective experience of immigration with voting for the populist radical right