Plasma Enhanced Chemical Vapor Deposition of Silicon Nitride and Oxynitride Films Using Disilane as Silicon Source.

Process characterization details along with the electrical properties of plasma enhanced chemical vapor deposited silicon nitride and oxynitride films are reported, for the first time, using disilane as the silicon source. Two regimes of deposition, namely excess-disilane regime and excess-ammonia regime, were observed for deposition of silicon nitride films using disilane, ammonia and helium. Films deposited under process conditions falling at the boundary of these two regimes had deposition rates that were mostly dependent on rf power and gas flow ratio resulting in highly repeatable film qualities. Silicon nitride films deposited on Si wafers at 250°C and post-metallization annealed in N2 ambient at 420°C exhibited fixed effective interface charge density of ∼3 x 1011 cm-2 and minimum interface state density of 2--3 x 1011cm -2 eV-1. The net bulk and interface charge density, charge trap density, interface trap density in the midbandgap region, and leakage current through the films were all lower for films that received a post-metallization anneal in both N2 and forming gas ambients compared to the values for films annealed in either N2 or forming gas ambients alone. All films exhibited higher instability due to hole trapping under negative gate bias stressing than due to electron trapping under positive gate bias stressing. Silicon oxynitride films were deposited by introducing N2O gas into the disilane/ammonia/helium gas system. Films deposited using higher N2O flow rates exhibited higher net effective fixed interface charge densities. The charge trapping in the films decreased with increasing N 2O flow rates employed in deposition except at the highest N2O flow rate investigated. In general, a turn-around behavior was observed in the trend for several electrical properties of the oxynitride films with increasing N2O flow rates. All the oxynitride films examined exhibited fewer occurrences of extrinsic breakdown compared to silicon nitride films, indicating reduction of pinhole density in the oxynitride films. Reviewing the overall properties of these films, it was deduced that the silicon oxynitride films deposited using NH3 to N2O flow rate of 20 in the present system would be the most practical choice for their use as gate dielectric films in thin film transistor applications

Development of plasma enhanced chemical vapor deposition (PECVD) gate dielectrics for TFT applications

This study investigated a variety of electrically insulating materials for potential use as a gate dielectric in thin-film transistor applications. The materials that were investigated include silicon dioxide and oxynitride films deposited using PECVD and LPCVD techniques. Silicon source materials included tetraethylorthosilicate (TEOS) and silane (SiH4). Oxygen sources included diatomic oxygen (O2) and nitrous oxide (N2O). The optical, electrical, and material properties of the dielectrics were analyzed using Variable Angle Spectroscopic Ellipsometry (VASE), Fourier Transform Infrared Spectroscopy (FTIR), Capacitance-Voltage (C-V) analysis and current-voltage (I-V) analysis. Transistors were also fabricated at low temperatures with different gate dielectrics to investigate the impact on device performance. While a deposited gate dielectric is intrinsically inferior to a thermally grown SiO2 layer, an objective of this study was to create a high quality gate dielectric with low levels of bulk and interface charge (Qit & Qot~1x1010 cm2); this was achieved

Investigation of Sputtered Hafnium Oxides for Gate Dielectric Applications in Integrated Circuits

This work investigated high permittivity hafnium based dielectric films for use in future generation metal oxide semiconductor field-effect transistor (MOSFET) technologies. For the sub- 100 nm MOS structure, the conventional Si02 gate dielectric required is becoming too thin ( Two deposition processes were used for investigating hafnium oxide: A traditional reactive sputtering process using a hafnium target and oxygen along with a metal oxidation process in which hafnium metal was deposited and subsequently oxidized in a rapid thermal processor. The films and their interfacial layers were studied using transmission electron microscopy and Rutherford backscattering. Suppression of the interfacial layers was attempted by utilizing various pre-deposition cleaning processes, nitrogen incorporation, and multiple annealing conditions. Statistical analysis was performed on many film properties including: thickness and refractive index by ellipsometry, equivalent oxide thickness (EOT), relative permittivity (sr), total charge density (Nss) via capacitance-voltage analysis (C-V), oxide charge density (Qox) and interface trap charge density (DiT) from surface charge analysis, and breakdown strength vi and leakage current density from current-voltage analysis (I-V). Hafnium oxide was successfully integrated into an RIT sub-micron NMOS process, and operational 0.5 um transistors were fabricated and tested

Preparation and properties of high dose nitrogen implanted epitaxially grown gadolinium oxide on silicon

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Process development and reliability of thin gate oxides

The Semiconductor Industry Association\u27s (SIA) current National Technological Roadmap calls for the development of a suitable dielectric material for use in gate oxide for the 0.18|micrometers generation of chips and beyond. Some of the key challenges identified are resistance to oxide trapped charge generation from higher levels of tunneling currents and/or plasma processing, and formation of an effective barrier to dopant penetration during the gate processing. One promising material to meet these challenges is nitrided thermal oxide. Development of a growth process that yields high quality, lOnm thick, thermally grown Si02 films at RJT for use as a gate dielectric is described. Thin oxides (8nm - 20nm) were grown by thermal oxidation followed by inert anneals in Ar and N2. Nitrided oxides were created by implanting N2 (dose range: 5el3 - lei 5 /cm2) into the substrate prior to gate oxidation. Test equipment was setup to study Fowler Nordheim (FN) tunneling and dielectric breakdown. Test structures consisted of conventional and novel MOS capacitor structures with aluminum and poly-silicon gate electrodes. Scaling RJT\u27s existing, 20nm oxidation process to lOnm resulted in degradation of dielectric strength from \u3e lOMV/cm to ~6-7MV/cm for Al-gate MOS capacitors. Replacing the Al gate material with poly-silicon restored the dielectric strength to lOMV/cm. Performing an N2 implant through a screening oxide, prior to gate oxidation, was investigated as a means of obtaining a nitrided thermal oxide. For certain doses (5el3 - 5el4 /cm2), Al-gate MOS capacitors exhibited an improved dielectric strength as the mean value increased from 6- 7MV/cm to ~9MV/cm. Poly-Si gate MOS capacitors showed a similar improvement for the nitrided oxides, exhibiting mean dielectric strength values in the 10-12MV/cm range. Fowler- Nordheim (FN) tunnel current measurements showed that the nitrided films exhibit lower leakage levels and less charge trapping than their thermal Si02 counterparts. Results indicate that a 12nm nitrided oxide, for a certain dose (5el4/cm2), exhibited equivalent electrical performance to a 20nm thermally grown Si02 oxide. In conclusion, a process was developed for yielding reliable thin gate oxides (~10nm) in a university fab

Chemical vapor deposition and characterization of polysilanes polymer based thin films and their applications in compound semiconductors and silicon devices

As the semiconductors industry is moving toward nanodevices, there is growing need to develop new materials and thin films deposition processes which could enable strict control of the atomic composition and structure of thin film materials in order to achieve precise control on their electrical and optical properties. The accurate control of thin film characteristics will become increasingly important as the miniaturization of semiconductor devices continue. There is no doubt that chemical synthesis of new materials and their self assembly will play a major role in the design and fabrication of next generation semiconductor devices. The objective of this work is to investigate the chemical vapor deposition (CVD) process of thin film using a polymeric precursor as a source material. This process offers many advantages including low deposition cost, hazard free working environment, and most importantly the ability to customize the polymer source material through polymer synthesis and polymer functionalization. The combination between polymer synthesis and CVD process will enable the design of new generation of complex thin film materials with a wide range of improved chemical, mechanical, electrical and optical properties which cannot be easily achieved through conventional CVD processes based on gases and small molecule precursors. In this thesis we mainly focused on polysilanes polymers and more specifically poly(dimethylsilanes). The interest in these polymers is motivated by their distinctive electronic and photonic properties which are attributed to the delocalization of the [sigma]-electron along the Si-Si backbone chain. These characteristics make polysilane polymers very promising in a broad range of applications as a dielectric, a semiconductor and a conductor. The polymer-based CVD process could be eventually extended to other polymer source materials such as polygermanes, as well as and a variety of other inorganic and hybrid organic-inorganic polymers. This work has demonstrated that a polysilane polymeric source can be used to deposit a wide range of thin film materials exhibiting similar properties with conventional ceramic materials such as silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC) silicon dioxide (SiO[subscript 2]) and silicon nitride (Si[subscipt 3]N[subscript 4]). The strict control of the deposition process allows precise control of the electrical, optical and chemical properties of polymer-based thin films within a broad range. This work has also demonstrated for the first time that poly(dimethylsilmaes) polymers deposited by CVD can be used to effectively passivate both silicon and gallium arsenide MOS devices. This finding makes polymer-based thin films obtained by CVD very promising for the development of high-[kappa] dielectric materials for next generation high-mobility CMOS technology

HfO2 as gate dielectric on Si and Ge substrate

Hafnium oxide HfO2 has been considered as an alternative to silicon dioxide SiO2 in future nano-scale complementary metal-oxide-semiconductor (CMOS) devices since it provides the required capacitance at the reduced device size because of its high dielectric constant. HfO2 films are currently deposited by various techniques. Many of them require high temperature annealing that can impact device performance and reliability. In this research, electrical characteristics of capacitors with HfO2 as gate dielectric deposited by standard thermal evaporation and e-beam evaporation on Si and Ge substrates were investigated. The dielectric constant of HfO2 deposited by thermal evaporation on Si is in the range of 18-25. Al/HfO2/Si MOS capacitors annealed at 450°C show low hysteresis, leakage current density and bulk oxide charges. Interface state density and low temperature charge trapping behavior of these structures were also investigated. Degradation in surface carrier mobility has been reported in Si field-effect-transistors with HfO2 as gate dielectric. To explore the possibility of alleviating this problem we have used germanium (Ge) substrate as this semiconductor has higher carrier mobility than Si. Devices fabricated by depositing HfO2 directly on Ge by standard thermal evaporation were found to be too leaky and show significant hysteresis and large shift in flatband voltage. This deterioration in electrical performance is mainly due to the formation of unstable interfacial layer of GeO2 during the HfO2 deposition. To minimize this effect, Ge surface was treated with the beam of atomic nitrogen prior to the dielectric deposition. The effect of surface nitridation, on interface as well as on bulk oxide, trap energy levels were investigated using low temperature C-V measurements. They revealed additional defect levels in the nitrided devices indicating diffusion of nitrogen from interface into the bulk oxide. Impact of surface nitridation on the reliability of Ge/HfO2/Al MOS capacitors has been investigated by application of constant voltage stress at different voltage levels for various time periods. It was observed that deeper trap levels in nitrided devices, found from low frequency and low temperature measurements, trap the charge carrier immediately after stress but with time these carriers detrap and create more traps inside the bulk oxide resulting in further devices deterioration. It is inferred that though nitrogen is effective in reducing interfacial layer growth it incorporates more defects at interface as well as in bulk oxide. Therefore, it is important to look into alternative methods of surface passivation to limit the growth of GeO2 at the interface

Advanced gate stack for sub-0.1 (mu)m CMOS technology

Ph.DDOCTOR OF PHILOSOPH