1,296 research outputs found
An asynchronous instruction length decoder
Journal ArticleThis paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocessor architecture. A prototype complex instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium® Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II® 32-bit MMX instruction set.] The prototype chip was fabricated on a 0.25-CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 instructions per nanosecond-with manageable risks using this design technology. The prototype achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as the fastest commercial 400-MHz clocked circuit fabricated on the same process
Towards Real-Time, On-Board, Hardware-Supported Sensor and Software Health Management for Unmanned Aerial Systems
For unmanned aerial systems (UAS) to be successfully deployed and integrated within the national airspace, it is imperative that they possess the capability to effectively complete their missions without compromising the safety of other aircraft, as well as persons and property on the ground. This necessity creates a natural requirement for UAS that can respond to uncertain environmental conditions and emergent failures in real-time, with robustness and resilience close enough to those of manned systems. We introduce a system that meets this requirement with the design of a real-time onboard system health management (SHM) capability to continuously monitor sensors, software, and hardware components. This system can detect and diagnose failures and violations of safety or performance rules during the flight of a UAS. Our approach to SHM is three-pronged, providing: (1) real-time monitoring of sensor and software signals; (2) signal analysis, preprocessing, and advanced on-the-fly temporal and Bayesian probabilistic fault diagnosis; and (3) an unobtrusive, lightweight, read-only, low-power realization using Field Programmable Gate Arrays (FPGAs) that avoids overburdening limited computing resources or costly re-certification of flight software. We call this approach rt-R2U2, a name derived from its requirements. Our implementation provides a novel approach of combining modular building blocks, integrating responsive runtime monitoring of temporal logic system safety requirements with model-based diagnosis and Bayesian network-based probabilistic analysis. We demonstrate this approach using actual flight data from the NASA Swift UAS
Specification and validation of control-intensive integrated circuits in hopCP
technical reportControl intensive ICs pose a significant challenge to the users of formal methods in designing hardware. These ICs have to support a wide variety of requirements including synchronous and asynchronous operations, polling and interrupt-driven modes of operation, multiple concurrent threads of execution, complex computations, and programmability. In this paper, we illustrate the use of formal methods in the design of a control intensive IC called the "Intel 8251" Universal Synchronous/Asynchronous Receiver/Transmitter (USART), using our formal hardware description language 'hopCP'. A feature of hopCP is that it supports communication via asynchronous ports (distributed shared variables writable by exactly one process), in addition to synchronous message passing. We show the usefulness of this combination of communication constructs. We outline static analysis algorithms to determine safe usages of asynchronous ports, and also to discover other static properties of the specification. We discuss a compiled-code concurrent functional simulator called CFSIM, as well as the use of concurrent testers for driving CFSIM. The use of a seraantically well specified and simple language, and the associated analysis/simulation tools helps conquer the complexity of specifying and validating control intensive ICs
MGSim - Simulation tools for multi-core processor architectures
MGSim is an open source discrete event simulator for on-chip hardware
components, developed at the University of Amsterdam. It is intended to be a
research and teaching vehicle to study the fine-grained hardware/software
interactions on many-core and hardware multithreaded processors. It includes
support for core models with different instruction sets, a configurable
multi-core interconnect, multiple configurable cache and memory models, a
dedicated I/O subsystem, and comprehensive monitoring and interaction
facilities. The default model configuration shipped with MGSim implements
Microgrids, a many-core architecture with hardware concurrency management.
MGSim is furthermore written mostly in C++ and uses object classes to represent
chip components. It is optimized for architecture models that can be described
as process networks.Comment: 33 pages, 22 figures, 4 listings, 2 table
Ohjaus- ja tiedonkeruuohjelma automaattiseen integroitujen piirien evaluointiin
Automatic evaluation of integrated circuits can provide significant benefits and savings for a company compared to doing the evaluation manually. This paper describes a LabVIEW application called ATAC that was developed to automate evaluation of ASIC circuits. The same software can also be used to test integrated circuits in general in different hardware environments.
A hardware setup for automatic ASIC evaluation is presented and it is used as basis for ATAC design. Presented software application ATAC can be used to control all hardware components in the evaluation setup but it can also be used without the hardware components. Hardware abstraction in ATAC makes it possible to use the same software solution in different environments with little modifications to the software code. The process of developing ATAC is presented as well as final application.
Screenshots of GUI are presented as well as the underlying code using state chart presentation. The software was reviewed and assessed by end users who performed several ASIC evaluation tests using ATAC during the software development. An example case of an ASIC evaluation test is presented and the measurement results gathered with ATAC are discussed.Integroitujen piirien automaattinen evaluointi voi tuottaa huomattavia etuja ja säästöjä yhtiölle verrattuna evaluoinnin manuaaliseen suorittamiseen. Tässä opinnäytetyössä esitellään LabVIEW-sovellus nimeltään ATAC, joka kehitettiin automatisoimaan ASIC-piirien evaluointi. Samaa sovellusta voi käyttää myös muiden integroitujen piirien testaukseen erilaisissa laitteistoympäristöissä.
Laitteisto ASIC-piirien automaattista evaluointia varten esitellään ja tämän laitteiston käyttöön ATAC lähtökohtaisesti suunniteltiin. Esitettyä ohjelmaa voi käyttää laitteiston kaikkien osien kontrollointiin, mutta ohjelmaa voi käyttää myös ilman laitteistokomponentteja. Laitteiston abstrahointi ATAC:ssa mahdollistaa ATAC:n käytön eri ympäristöissä ilman suuria muutoksia ohjelmakoodiin. ATAC:n kehitysprosessi sekä lopullinen ohjelma esitellään tässä opinnäytetyössä.
Graafinen käyttöliittymä esitellään kuvakaappausten avulla ja koodi kuvaillaan käyttäen tilakaavioita. Ohjelman käytettävyyttä ja ohjelmankehitysprojektin onnistuneisuutta arvioidaan loppukäyttäjien kokemusten sekä todellisten ASIC-piirien evaluointimittausten tulosten perusteella. Esimerkki ASIC-piirin evaluointitestistä esitetään ja ATAC:n keräämiä mittaustuloksia arvioidaan
Applications for FPGA's on Nanosatellites
This thesis examines the feasibility of using a Field Programmable Gate Array (FPGA) based design on-board a CubeSat-sized nanosatellite. FPGAs are programmable logic devices that allow for the implementation of custom digital hardware on a single Integrated Circuit (IC). By using these FPGAs in spacecraft, more efficient processing can be done by moving the design onto hardware. A variety of different FPGA-based designs are looked at, including a Watchdog Timer (WDT), a Global Positioning System (GPS) receiver, and a camera interface
RAID-2: Design and implementation of a large scale disk array controller
We describe the implementation of a large scale disk array controller and subsystem incorporating over 100 high performance 3.5 inch disk drives. It is designed to provide 40 MB/s sustained performance and 40 GB capacity in three 19 inch racks. The array controller forms an integral part of a file server that attaches to a Gb/s local area network. The controller implements a high bandwidth interconnect between an interleaved memory, an XOR calculation engine, the network interface (HIPPI), and the disk interfaces (SCSI). The system is now functionally operational, and we are tuning its performance. We review the design decisions, history, and lessons learned from this three year university implementation effort to construct a truly large scale system assembly
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