Control analysis and design of medium voltage converter with multirate techniques

This work aims to unify the current knowledge about multirate controllers with design techniques for grid-tied converters, in this occasion, connected to Medium Voltage AC grid. Therefore, the multirate contributions, that have been given so far, are studied, as well as everything related to modulation techniques for power converters. The temporal implications of the DSPWM actuator will be correlated to multirate analysis, in addition to possible alternatives for applications with a lower sampling frequency than modulation one. Finalizing with explanations and result demonstrations of controllers working between two frequencies or rates, by means of the available power converter in laboratory.Este trabajo pretende unir el conocimiento actual sobre controladores multitasa o multifrecuencia (multirate) con técnicas de diseño para convertidores conectados a la red, en este caso concreto, a la red alterna (AC) de Media Tensión. Por tanto, se estudian las contribuciones multirate realizadas hasta la fecha, así como todo lo relacionado con la modulación de la señal de control para los convertidores. Las implicaciones temporales del actuador DSPWM se relacionarán con el análisis multitasa, así como se explicarán posibles alternativas para aplicaciones con una frecuencia de muestreo menor que la de modulación. Finalizando con la explicación y presentación de resultados de controladores trabajando entre dos frecuencias o tasas, mediante simulaciones del convertidor disponible en laboratorio.Máster Universitario en Ingeniería Industrial (M141

Complex-based controller for a three-phase inverter with an LCL filter connected to unbalanced grids

A new controller for a grid-connected inverter with an LCL filter is proposed in this paper. The system is described by its complex representation, and the controller is designed using the complex root locus method. The complex representation allows a considerable reduction in the order of the system, simplifying the design task and making it possible to use advanced techniques, such as the complex root locus. The new complex controller adds an extra degree of freedom that makes it possible to move the poles of the systems and to improve the stability and speed of response compared with the conventional controls. This paper includes a detailed discussion of the effect of the gains of the controller on the root locus. The proposal is validated with simulation and experimental results.Fil: Doria Cerezo, Arnau. Universidad Politécnica de Catalunya; EspañaFil: Serra, Federico Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - San Luis. Instituto de Investigaciones en Tecnología Química. Universidad Nacional de San Luis. Facultad de Química, Bioquímica y Farmacia. Instituto de Investigaciones en Tecnología Química; ArgentinaFil: Bodson, Marc. University of Utah; Estados Unido

Strategies towards high performance (high-resolution/linearity) time-to-digital converters on field-programmable gate arrays

Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility, and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required.Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility, and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required