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    New Protograph-Based Construction of GLDPC Codes for Binary Erasure Channel and LDPC Codes for Block Fading Channel

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    ํ•™์œ„๋…ผ๋ฌธ(๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2022.2. ๋…ธ์ข…์„  ๊ต์ˆ˜๋‹˜.์ด ํ•™์œ„ ๋…ผ๋ฌธ์—์„œ๋Š” ๋‹ค์Œ ๋‘ ๊ฐ€์ง€์˜ ์—ฐ๊ตฌ๊ฐ€ ์ด๋ฃจ์–ด์กŒ๋‹ค: i) ์ด์ง„ ์†Œ์‹ค ์ฑ„๋„์—์„œ ์ƒˆ๋กœ์šด ๊ตฌ์กฐ์˜ ํ”„๋กœํ† ๊ทธ๋ž˜ํ”„ ๊ธฐ๋ฐ˜ generalized low-density parity-check (GLDPC) ๋ถ€ํ˜ธ์˜ ์„ค๊ณ„ ๋ฐฉ๋ฒ• ii) ๋ธ”๋ก ํŽ˜์ด๋”ฉ ์ฑ„๋„์„ ์œ„ํ•œ ํ”„๋กœํ† ๊ทธ๋ž˜ํ”„ ๊ธฐ๋ฐ˜์˜ LDPC ๋ถ€ํ˜ธ ์„ค๊ณ„. ์ฒซ ๋ฒˆ์งธ๋กœ, ์ด์ง„ ์†Œ์‹ค ์ฑ„๋„์—์„œ ์ƒˆ๋กญ๊ฒŒ ์ œ์•ˆ๋œ ๋ถ€๋ถ„์  ๋„ํ•‘ ๊ธฐ๋ฒ•์„ ์ด์šฉํ•œ ํ”„๋กœํ† ๊ทธ๋ž˜ํ”„ ๊ธฐ๋ฐ˜์˜ GLDPC ๋ถ€ํ˜ธ๊ฐ€ ์ œ์•ˆ๋˜์—ˆ๋‹ค. ๊ธฐ์กด์˜ ํ”„๋กœํ† ๊ทธ๋ž˜ํ”„ ๊ธฐ๋ฐ˜์˜ GLDPC ๋ถ€ํ˜ธ์˜ ๊ฒฝ์šฐ ํ”„๋กœํ† ๊ทธ๋ž˜ํ”„ ์˜์—ญ์—์„œ single parity-check (SPC) ๋…ธ๋“œ๋ฅผ generalized constraint (GC) ๋…ธ๋“œ๋กœ ์น˜ํ™˜(๋„ํ•‘)ํ•˜๋Š” ํ˜•ํƒœ๋กœ ๋ถ€ํ˜ธ๊ฐ€ ์„ค๊ณ„๋˜์–ด ์—ฌ๋Ÿฌ ๋ณ€์ˆ˜ ๋…ธ๋“œ ๊ฑธ์ณ GC ๋…ธ๋“œ๊ฐ€ ์—ฐ๊ฒฐ๋˜๋Š” ํ˜•ํƒœ๋ฅผ ๊ฐ€์ง„๋‹ค. ๋ฐ˜๋ฉด, ์ œ์•ˆ๋œ ๋ถ€๋ถ„์  ๋„ํ•‘ ๊ธฐ๋ฒ•์€ ํ•œ ๊ฐœ์˜ ๋ณ€์ˆ˜ ๋…ธ๋“œ์— GC ๋…ธ๋“œ๋ฅผ ์—ฐ๊ฒฐํ•˜๋„๋ก ๋งŒ๋“ค ์ˆ˜ ์žˆ๋‹ค. ๋ฐ”๊ฟ” ๋งํ•˜๋ฉด, ์ œ์•ˆ๋œ ๋ถ€๋ถ„์  ๋„ํ•‘ ๊ธฐ๋ฒ•์€ ๋” ์„ธ๋ฐ€ํ•œ ๋„ํ•‘์ด ๊ฐ€๋Šฅํ•ด์„œ ๊ฒฐ๊ณผ์ ์œผ๋กœ ๋ถ€ํ˜ธ ์„ค๊ณ„์— ์žˆ์–ด ๋†’์€ ์ž์œ ๋„๋ฅผ ๊ฐ€์ง€๊ณ  ๋” ์„ธ๋ จ๋œ ๋ถ€ํ˜ธ ์ตœ์ ํ™”๊ฐ€ ๊ฐ€๋Šฅํ•˜๋‹ค. ๋ณธ ํ•™์œ„ ๋…ผ๋ฌธ์—์„œ๋Š” ๋ถ€๋ถ„์  ๋„ํ•‘๊ณผ PEXIT ๋ถ„์„์„ ์ด์šฉํ•˜์—ฌ partially doped GLDPC (PD-GLDPC) ๋ถ€ํ˜ธ๋ฅผ ์„ค๊ณ„ํ•˜๊ณ  ์ตœ์ ํ™” ํ•˜์˜€๋‹ค. ๋”๋ถˆ์–ด, PD-GLDPC ๋ถ€ํ˜ธ์˜ ์ผ๋ฐ˜์  ์ตœ์†Œ ๊ฑฐ๋ฆฌ๋ฅผ ๊ฐ€์ง€๋Š” ์กฐ๊ฑด์„ ์ œ์‹œํ•˜์˜€๊ณ  ์ด๋ฅผ ์ด ๋ก ์ ์œผ๋กœ ์ฆ๋ช…ํ•˜์˜€๋‹ค. ๊ฒฐ๊ณผ์ ์œผ๋กœ, ์ œ์•ˆ๋œ PD-GLDPC ๋ถ€ํ˜ธ๋Š” ํ˜„์กดํ•˜๋Š” GLDPC ๋ถ€ํ˜ธ์˜ ์„ฑ๋Šฅ๋ณด๋‹ค ์œ ์˜๋ฏธํ•˜๊ฒŒ ์›Œํ„ฐํ”Œ ์„ฑ๋Šฅ์ด ์ข‹์•˜๊ณ  ๋™์‹œ์— ์˜ค๋ฅ˜ ๋งˆ๋ฃจ๊ฐ€ ์—†์—ˆ๋‹ค. ๋งˆ์ง€๋ง‰์œผ๋กœ, ์ตœ์ ํ™”๋œ PD-GLDPC ๋ถ€ํ˜ธ๋Š” ํ˜„์กดํ•˜๋Š” ์ตœ์‹  ๋ธ”๋ก LDPC ๋ถ€ํ˜ธ๋“ค์— ๊ทผ์ ‘ํ•œ ์„ฑ๋Šฅ์„ ๊ฐ€์ง์„ ๋ณด์—ฌ์ฃผ์—ˆ๋‹ค. ๋‘ ๋ฒˆ์งธ๋กœ, ๋ธ”๋ก ํŽ˜์ด๋”ฉ (BF) ์ฑ„๋„์—์„œ resolvable block design (RBD)๋ฅผ ์ด์šฉํ•œ ํ”„๋กœํ† ๊ทธ๋ž˜ํ”„ LDPC ๋ถ€ํ˜ธ ์„ค๊ณ„๊ฐ€ ์ด๋ฃจ์–ด์กŒ๋‹ค. ์ œ์•ˆ๋œ ๋ถ€ํ˜ธ์˜ ์„ฑ๋Šฅ์„ ํ™•์ธํ•˜๊ธฐ ์œ„ํ•œ ๋น„ํŠธ ์˜ค๋ฅ˜์œจ์˜ ์ƒํ•œ์„ ๊ฐ๋งˆ ์ง„ํ™”๋ผ๋Š” ์ œ์•ˆ๋œ ๊ธฐ๋ฒ•์„ ์ด์šฉํ•ด ์œ ๋„ํ•˜์˜€๋‹ค. ๋˜ํ•œ, ์‹œ๋ฎฌ๋ ˆ์ด์…˜์„ ํ†ตํ•ด ์œ ๋„๋œ ์˜ค๋ฅ˜์œจ ์ƒํ•œ๊ณผ ๋ถ€ํ˜ธ์˜ ํ”„๋ ˆ์ž„ ์˜ค๋ฅ˜์œจ์ด ๋†’์€ SNR ์˜์—ญ์—์„œ ์ฑ„๋„ outage ํ™•๋ฅ ์— ๊ทผ์ ‘ํ•จ์„ ์•Œ ์ˆ˜ ์žˆ๋‹ค.In this dissertation, two main contributions are given as: i) new construction methods for protograph-based generalized low-density parity-check (GLDPC) codes for the binary erasure channel using partial doping technique and ii) new design of protograph-based low-density parity-check (LDPC) codes for the block fading channel using resolvable block design. First, a new code design technique, called partial doping, for protograph-based GLDPC codes is proposed. While the conventional construction method of protograph-based GLDPC codes is to replace some single parity-check (SPC) nodes with generalized constraint (GC) nodes applying to multiple connected variable nodes (VNs) in the protograph, the proposed technique of partial doping can select any number of partial VNs in the protograph to be protected by GC nodes. In other words, the partial doping technique enables finer tuning of doping, which gives higher degrees of freedom in the code design and enables a sophisticated code optimization. The proposed partially doped GLDPC (PD-GLDPC) codes are constructed using the partial doping technique and optimized by the protograph extrinsic information transfer (PEXIT) analysis. In addition, the condition guaranteeing the linear minimum distance growth of the PD-GLDPC codes is proposed and analytically proven so that the PD-GLDPC code ensembles satisfying this condition have the typical minimum distance. Consequently, the proposed PD-GLDPC codes outperform the conventional GLDPC codes with a notable improvement in the waterfall performance and without the error floor phenomenon. Finally, the PD-GLDPC codes are shown to achieve a competitive performance compared to the existing state-of-the-art block LDPC codes. Second, the protograph-based LDPC codes constructed from resolvable balanced incomplete block design (RBIBD) are designed and proposed for block fading (BF) channel. In order to analyze the performance of the proposed LDPC codes, the upper bounds on bit error rate (BER) using the novel method called gamma evolution are derived. In addition, the numerical analysis shows that the upper bound and the frame error rate (FER) of the proposed LDPC codes approach the channel outage probability in a finite signal-to-noise ratio (SNR) region.1 INTRODUCTION 1 1.1 Background 1 1.2 Overview of Dissertation 3 2 Overview of LDPC Codes 5 2.1 LDPC Codes 5 2.2 Decoding of LDPC Codes in the BEC 7 2.3 Analysis tool for LDPC Codes 8 2.3.1 Density Evolution 8 2.4 Protograph-Based LDPC Codes 9 3 Construction of Protograph-Based Partially Doped Generalized LDPC Codes 11 3.1 Code Structure of Protograph-Based GLDPC Ensembles 14 3.1.1 Construction of Protograph Doped GLDPC Codes 14 3.1.2 PEXIT Analysis and Decoding Process of Protograph Doped GLDPC Codes 15 3.2 The Proposed PD-GLDPC Codes 18 3.2.1 Construction Method of PD-GLDPC Codes 18 3.2.2 PEXIT Analysis of PD-GLDPC Codes 22 3.2.3 Condition for the Existence of the Typical Minimum Distance of the PD-GLDPC Code Ensemble 23 3.2.4 Comparison between Proposed PD-GLDPC Codes and Protograph Doped GLDPC Codes 25 3.3 Optimization of PD-GLDPC Codes 26 3.3.1 Construction of PD-GLDPC Codes from Regular Protographs 26 3.3.2 Differential Evolution-Based Code Construction from the Degree Distribution of Random LDPC Code Ensembles 28 3.3.3 Optimization of PD-GLDPC Codes Using Protograph Differential Evolution 32 3.4 Numerical Results and Analysis 36 3.4.1 Simulation Result for Optimized PD-GLDPC Code from Regular and Irregular Random LDPC Code Ensembles 36 3.4.2 Simulation Result for PD-GLDPC Code from Optimized Protograph 43 3.5 Proof of Theorem 1: The Constraint for the Existence of the Typical Minimum Distance of the Proposed Protograph-Based PD-GLDPC Codes 45 4 Design of Protograph-Based LDPC Code Using Resolvable Block Design for Block Fading Channel 52 4.1 Problem Formulation 53 4.1.1 BF Channel Model 53 4.1.2 Performance Metrics of BF Channel 54 4.1.3 Protograph-Based LDPC Codes and QC LDPC Codes 57 4.2 New Construction of Protograph-Based LDPC Codes from Resolvable Block Designs 57 4.2.1 Resolvable Block Designs 57 4.2.2 Construction of the Proposed Protograph-Based LDPC Codes 59 4.2.3 Theoretical Analysis of the Proposed Protograph-Based LDPC Code from RBD 61 4.2.4 Numerical Analysis of the Proposed Protograph-Based LDPC Code Codes for BF Channel 65 4.2.5 BER Comparison with Analytical Results from Gamma Evolution 65 4.2.6 FER Comparison with Channel Outage Probability 67 5 Conclusions 69 Abstract (In Korean) 78๋ฐ•

    Fault Secure Encoder and Decoder for NanoMemory Applications

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    Memory cells have been protected from soft errors for more than a decade; due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected. We introduce a new approach to design fault-secure encoder and decoder circuitry for memory designs. The key novel contribution of this paper is identifying and defining a new class of error-correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple. We further quantify the importance of protecting encoder and decoder circuitry against transient errors, illustrating a scenario where the system failure rate (FIT) is dominated by the failure rate of the encoder and decoder. We prove that Euclidean geometry low-density parity-check (EG-LDPC) codes have the fault-secure detector capability. Using some of the smaller EG-LDPC codes, we can tolerate bit or nanowire defect rates of 10% and fault rates of 10^(-18) upsets/device/cycle, achieving a FIT rate at or below one for the entire memory system and a memory density of 10^(11) bit/cm^2 with nanowire pitch of 10 nm for memory blocks of 10 Mb or larger. Larger EG-LDPC codes can achieve even higher reliability and lower area overhead

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    This paper presents a practical method of potential replacement of several different Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to implement the LDPC encoder and decoder in a memory-constrained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algorithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the proposed LDPC setup simplification. Finally, the error performance of the modified system structure is evaluated and compared with the original system structure by means of simulation

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    Polar codes are a recently proposed family of provably capacity-achieving error-correction codes that received a lot of attention. While their theoretical properties render them interesting, their practicality compared to other types of codes has not been thoroughly studied. Towards this end, in this paper, we perform a comparison of polar decoders against LDPC and Turbo decoders that are used in existing communications standards. More specifically, we compare both the error-correction performance and the hardware efficiency of the corresponding hardware implementations. This comparison enables us to identify applications where polar codes are superior to existing error-correction coding solutions as well as to determine the most promising research direction in terms of the hardware implementation of polar decoders.Comment: Fixes small mistakes from the paper to appear in the proceedings of IEEE WCNC 2017. Results were presented in the "Polar Coding in Wireless Communications: Theory and Implementation" Worksho

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    Centralized Radio Access Network (C-RAN) is a new paradigm for wireless networks that centralizes the signal processing in a computing cloud, allowing commodity computational resources to be pooled. While C-RAN improves utilization and efficiency, the computational load occasionally exceeds the available resources, creating a computational outage. This paper provides a mathematical characterization of the computational outage probability for low-density parity check (LDPC) codes, a common class of error-correcting codes. For tractability, a binary erasures channel is assumed. Using the concept of density evolution, the computational demand is determined for a given ensemble of codes as a function of the erasure probability. The analysis reveals a trade-off: aggressively signaling at a high rate stresses the computing pool, while conservatively backing-off the rate can avoid computational outages. Motivated by this trade-off, an effective computationally aware scheduling algorithm is developed that balances demands for high throughput and low outage rates.Comment: Conference on Information Sciences and Systems (CISS) 2017, to appea
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