Output-capacitorless segmented low-dropout voltage regulator with controlled pass transistors

This article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxide-semiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18¿µm CMOS process to supply a stable load current between 0 and 100¿mA with a 40¿pF on-chip output capacitor, while consuming 4.8¿µA quiescent current. The dropout voltage of the LDO is set to 200¿mV for 1.8¿V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively.Peer ReviewedPostprint (author's final draft

Ultra-Low Power Transmitter and Power Management for Internet-of-Things Devices

Two of the most critical components in an Internet-of-Things (IoT) sensing and transmitting node are the power management unit (PMU) and the wireless transmitter (Tx). The desire for longer intervals between battery replacements or a completely self-contained, battery-less operation via energy harvesting transducers and circuits in IoT nodes demands highly efficient integrated circuits. This dissertation addresses the challenge of designing and implementing power management and Tx circuits with ultra-low power consumption to enable such efficient operation. The first part of the dissertation focuses on the study and design of power management circuits for IoT nodes. This opening portion elaborates on two different areas of the power management field: Firstly, a low-complexity, SPICE-based model for general low dropout (LDO) regulators is demonstrated. The model aims to reduce the stress and computation times in the final stages of simulation and verification of Systems-on-Chip (SoC), including IoT nodes, that employ large numbers of LDOs. Secondly, the implementation of an efficient PMU for an energy harvesting system based on a thermoelectric generator transducer is discussed. The PMU includes a first-in-its-class LDO with programmable supply noise rejection for localized improvement in the suppression. The second part of the dissertation addresses the challenge of designing an ultra- low power wireless FSK Tx in the 900 MHz ISM band. To reduce the power consumption and boost the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator employed as the local oscillator generator scheme. In combination with an edge-combiner PA, the Tx showed a measured energy efficiency of 0.2 nJ/bit and a normalized energy efficiency of 3.1 nJ/(bit∙mW) when operating at output power levels up to -10 dBm and data rates of 3 Mbps. To close this dissertation, the implementation of a supply-noise tolerant BiCMOS ring-oscillator is discussed. The combination of a passive, high-pass feedforward path from the supply to critical nodes in the selected delay cell and a low cost LDO allow the oscillator to exhibit power supply noise rejection levels better than –33 dB in experimental results

Power-Efficient and High-Performance Cicruit Techniques for On-Chip Voltage Regulation and Low-Voltage Filtering

This dissertation focuses on two projects. The first one is a power supply rejection (PSR) enhanced with fast settling time (TS) bulk-driven feedforward (BDFF) capacitor-less (CL) low-dropout (LDO) regulator. The second project is a high bandwidth (BW) power adjustable low-voltage (LV) active-RC 4th -order Butterworth low pass filter (LPF). As technology improves, faster and more accurate LDOs with high PSR are going to be required for future on-chip applications and systems.The proposed BDFF CL-LDO will accomplish an improved PSR without degrading TS. This would be achieved by injecting supply noise through the pass device’s bulk terminal in order to cancel the supply noise at the output. The supply injection will be achieved by creating a feedforward path, which compared to feedback paths, that doesn’t degrade stability and therefore allows for faster dynamic performance. A high gain control loop would be used to maintain a high accuracy and dc performance, such as line/load regulation. The proposed CL-LDO will target a PSR better than – 90 dB at low frequencies and – 60 dB at 1 MHz for 50 mA of load current (IvL). The CL-LDO will target a loop gain higher than 90 dB, leading to an improved line and load regulation, and unity-gain frequency (UGF) higher than 20 MHz, which will allow a TS faster than 500 ns. The CL-LDO is going to be fabricated in a CMOS 130 nm technology; consume a quiescent current (IQ) of less than 50 μA; for a dropout voltage of 200 mV and an IvL of 50 mA. As technology scales down, speed and performance requirements increase for on-chip communication systems that reflect the current demand for high speed data-oriented applications. However, in small technologies, it becomes harder to achieve high gain and high speed at the same time because the supply voltage (VvDvD) decreases leaving no room for conventional high gain CMOS structures. The proposed active-RC LPF will accomplish a LV high BW operation that would allow such disadvantages to be overcome. The LPF will be implemented using an active RC structure that allows for the high linearity such communication systems demand. In addition, built-in BW and power configurability would address the demands for increased flexibility usually required in such systems. The proposed LV LPF will target a configurable cut-off frequency (ƒо) of 20/40/80/160 MHz with tuning capabilities and power adjustability for each ƒо. The filter will be fabricated in a CMOS 130 nm technology. The filter characteristics are as following: 4th -order, active-RC, LPF, Butterworth response, VDD = 0.6 V, THD higher than 40 dB and a third-order input intercept point (IIP3) higher than 10 dBm

Power Management Circuits for Front-End ASICs Employed in High Energy Physics Applications

The instrumentation of radiation detectors for high energy physics calls for the development of very low-noise application-specific integrated-circuits and demanding system-level design strategies, with a particular focus on the minimisation of inter-ference noise from power anagement circuitry. On the other hand, the aggressive pixelisation of sensors and associated front-end electronics, and the high radiation exposure at the innermost tracking and vertex detectors, requires radiation-aware design and radiation-tolerant deep sub-micron CMOS technologies. This thesis explores circuit design techniques towards radiation tolerant power management integrated circuits, targeting applications on particle detectors and monitoring of accelerator-based experiments, aerospace and nuclear applications. It addresses advantages and caveats of commonly used radiation-hard layout techniques, which often employ Enclosed Layout or H-shaped transistors, in respect to the use of linear transistors. Radiation tolerant designs for bandgap circuits are discussed, and two different topologies were explored. A low quiescent current bandgap for sub-1 V CMOS circuits is proposed, where the use of diode-connected MOSFETs in weak-inversion is explored in order to increase its radiation tolerance. An any-load stable LDO architecture is proposed, and three versions of the design using different layout techniques were implemented and characterised. In addition, a switched DC-DC Buck converter is also studied. For reasons concerning testability and silicon area, the controller of the Buck converter is on-chip, while the inductance and the power transistors are left on-board. A prototype test chip with power management IP blocks was fabricated, using a TSMC 65 nm CMOS technology. The chip features Linear, ELT and H-shape LDO designs, bandgap circuits and a Buck DC-DC converter. We discuss the design, layout and test results of the prototype. The specifications in terms of voltage range and output current capability are based on the requirements set for the integrated on-detector electronics of the new CGEM-IT tracker for the BESIII detector. The thesis discusses the fundamental aspects of the proposed on-detector electronics and provides an in-depth depiction of the front-end design for the readout ASIC

Output–capacitorless segmented low-dropout voltage regulator with controlled pass transistors

Peer Reviewe

Output–capacitorless segmented low–dropout voltage regulator with controlled pass transistors

This article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxide-semiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18¿µm CMOS process to supply a stable load current between 0 and 100¿mA with a 40¿pF on-chip output capacitor, while consuming 4.8¿µA quiescent current. The dropout voltage of the LDO is set to 200¿mV for 1.8¿V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively