Study of spin-scan imaging for outer planets missions

The constraints that are imposed on the Outer Planet Missions (OPM) imager design are of critical importance. Imager system modeling analyses define important parameters and systematic means for trade-offs applied to specific Jupiter orbiter missions. Possible image sequence plans for Jupiter missions are discussed in detail. Considered is a series of orbits that allow repeated near encounters with three of the Jovian satellites. The data handling involved in the image processing is discussed, and it is shown that only minimal processing is required for the majority of images for a Jupiter orbiter mission

Testing for delay defects utilizing test data compression techniques

textAs technology shrinks new types of defects are being discovered and new fault models are being created for those defects. Transition delay and path delay fault models are two such models that have been created, but they still fall short in that they are unable to obtain a high test coverage of smaller delay defects; these defects can cause functional behavior to fail and also indicate potential reliability issues. The first part of this dissertation addresses these problems by presenting an enhanced timing-based delay fault testing technique that incorporates the use of standard delay ATPG, along with timing information gathered from standard static timing analysis. Utilizing delay fault patterns typically increases the test data volume by 3-5X when compared to stuck-at patterns. Combined with the increase in test data volume associated with the increase in gate count that typically accompanies the miniaturization of technology, this adds up to a very large increase in test data volume that directly affect test time and thus the manufacturing cost. The second part of this dissertation presents a technique for improving test compression and reducing test data volume by using multiple expansion ratios while determining the configuration of the scan chains for each of the expansion ratios using a dependency analysis procedure that accounts for structural dependencies as well as free variable dependencies to improve the probability of detecting faults. Finally, this dissertation addresses the problem of unknown values (X’s) in the output response data corrupting the data and degrading the performance of the output response compactor and thus the overall amount of test compression. Four techniques are presented that focus on handling response data with large percentages of X’s. The first uses X-canceling MISR architecture that is based on deterministically observing scan cells, and the second is a hybrid approach that combines a simple X-masking scheme with the X-canceling MISR for further gains in test compression. The third and fourth techniques revolve around reiterative LFSR X-masking, which take advantage of LFSR-encoded masks that can be reused for multiple scan slices in novel ways.Electrical and Computer Engineerin

Optimization of Weight On Bit During Drilling Operation Based on Rate of Penetration Model

Drilling optimization is very important during drilling operation. Optimization of drilling could save time and cost of operation thus increases the profit. Drilling optimization aims to optimize controllable variables during drilling operation such as weight on bit and bit rotation speed for obtaining optimum drilling rate. In this project, Bourgoyne and Young ROP model has been selected to study the effects of several parameters during drilling operation. Important parameters such as depth, pore pressure, equivalent circulating density, bit weight, rotary speed, bit tooth wear, and jet impact force are extracted from drilling report. In order to study their relationship statistical method which is multiple regressions analysis has been used. The penetration model for the field is constructed using the results of statistical method. In the end, the result from analysis is used to determine optimum values of weight on bit that give optimize drilling operation. Overall, this project provides a study to the most complete mathematical model for rate of penetration that was constructed by Bourgoyne and Young. From the research the constants that represented several drilling variables had been determined. The rate of penetration for the field had been predicted based on the constants for every data depth. Finally, the optimized weight on bit had been calculated for the several data points and the results had been simulated using drilling simulator

Low-Capture-Power Test Generation for Scan-Based At-Speed Testing

Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR drop caused by high power dissipation when a test response is captured. This paper addresses this critical problem with a novel low-capture-power X-filling method of assigning 0\u27s and 1\u27s to unspecified (X) bits in a test cube obtained during ATPG. This method reduces the circuit switching activity in capture mode and can be easily incorporated into any test generation flow to achieve capture power reduction without any area, timing, or fault coverage impact. Test vectors generated with this practical method greatly improve the applicability of scan-based at-speed testing by reducing the risk of test yield lossIEEE International Conference on Test, 2005, 8 November 2005, Austin, TX, US

SUSTAINABLE SOIL MANAGEMENT IN NEW ZEALAND: FARMER BELIEFS, ATTITUDES AND MOTIVATIONS

Land Economics/Use,

Terrestrial applications: An intelligent Earth-sensing information system

For Abstract see A82-2214

Rate of Penetration Prediction Utilizing Hydromechanical Specific Energy

The prediction and the optimization of the rate of penetration (ROP), an important measure of drilling performance, have increasingly generated great interest. Several empirical techniques have been explored in the literature for the prediction and the optimization of ROP. In this study, four commonly used artificial intelligence (AI) algorithms are explored for the prediction of ROP based on the hydromechanical specific energy (HMSE) ROP model parameters. The AIs explored are the artificial neural network (ANN), extreme learning machine (ELM), support vector regression (SVR), and least-square support vector regression (LS-SVR). All the algorithms provided results with accuracy within acceptable range. The utilization of HMSE in selecting drilling variables for the prediction models provided an improved and consistent methodology of predicting ROP with drilling efficiency optimization objectives. This is valuable from an operational point of view, because it provides a reference point for measuring drilling efficiency and performance of the drilling process in terms of energy input and corresponding output in terms of ROP. The real-time drilling data utilized are must-haves, easily acquired, accessible, and controllable during drilling operations

In Situ Thermal Inspection of Automated Fiber Placement Operations for Tow and Ply Defect Detection

The advent of Automated Fiber Placement (AFP) systems have aided the rapid manufacturing of composite aerospace structures. One of the challenges that AFP systems pose is the uniformity of the deposited prepreg tape layers, which complicates detection of laps, gaps, overlaps and twists. The current detection method used in industry involves halting fabrication and performing a time consuming, visual inspection of each tape layer. Typical AFP systems use a quartz lamp to heat the base layer to make the surface tacky as it deposits another tape layer. The innovation proposed in this paper is to use the preheated base layer as a through-transmission heat source for inspecting the newly added tape layer in situ using a thermographic camera mounted on to the AFP hardware. Such a system would not only increase manufacturing throughput by reducing inspection times, but it would also aid in process development for new structural designs or material systems by providing data on as-built parts. To this end, a small thermal camera was mounted onto an AFP robotic research platform at NASA, and thermal data was collected during typical and experimental layup operations. The data was post processed to reveal defects such as tow overlap/gap, wrinkling, and peel-up. Defects that would have been impossible to detect visually were also discovered in the data, such as poor/loss of adhesion between plies and the effects of vacuum debulking. This paper will cover the results of our experiments, and the plans for future versions of this inspection system

Design of On-Chip Self-Testing Signature Register

Over the last few years, scan test has turn out to be too expensive to implement for industry standard designs due to increasing test data volume and test time. The test cost of a chip is mainly governed by the resource utilization of Automatic Test Equipment (ATE). Also, it directly depends upon test time that includes time required to load test program, to apply test vectors and to analyze generated test response of the chip. An issue of test time and data volume is increasingly appealing designers to use on-chip test data compactors, either on input side or output side or both. Such techniques significantly address the former issues but have little hold over increasing number of input-outputs under test mode. Further, test pins on DUT are increasing over the generations. Thus, scan channels on test floor are falling short in number for placement of such ICs. To address issues discussed above, we introduce an on-chip self-testing signature register. It comprises a response compactor and a comparator. The compactor compacts large chunk of response data to a small test signature whereas the comparator compares this test signature with desired one. The overall test result for the design is generated on single output pin. Being no storage of test response is demanded, the considerable reduction in ATE memory can be observed. Also, with only single pin to be monitored for test result, the number of tester channels and compare edges on ATE side significantly reduce at the end of the test. This cuts down maintenance and usage cost of test floor and increases its life time. Furthermore reduction in test pins gives scope for DFT engineers to increase number of scan chains so as to further reduce test time