Constant-gain envelope tracking in a UHF outphasing transmitter based on continuous-mode class-E GaN HEMT PAs

A UHF outphasing transmitter, based on continuous-mode class-E power amplifiers (PAs) and implementing a constant-gain envelope tracking (ET) strategy, is presented in this paper. Drain terminating and biasing networks are designed to provide near optima impedance values at the fundamental and higher order harmonics to the selected GaN HEMT device. A high-efficiency wideband performance, 80% for a 630-890 MHz range, is obtained, besides being amenable for load-modulation through a compact outphasing scheme, incorporating a series Chireix combiner and an impedance transformer. Once characterized in a pure output power phasecoding regime, the observed limitation in dynamic range is overcome by operating the amplifiers in a sort of continuous class-J mode, while forcing the load impedance to follow a constant-gain trajectory. A 1c-WCDMA signal, with peak-toaverage power ratio (PAPR) of 8.4 dB is shown to be reproduced, satisfying the linearity requirements, with an average efficiency of 58%.This work was supported by the Ministry of Economy and Competitiveness (MINECO) through TEC2014-58341-C4-1- R, TEC2014-58341-C4-2-R and TEC2014-58341-C4-3-R projects, co-funded with FEDER. José R. Pérez-Cisneros also thanks the support to his stay at the Univ. of Cantabria provided by the pre-doctoral mobility grant EEBB-I-15-10447

RF Power Amplifier and Its Envelope Tracking

This dissertation introduces an agile supply modulator with optimal transient performance for the envelope tracking supply in linear power amplifiers. For this purpose, an on-demand current source module, the bang-bang transient performance enhancer (BBTPE), is proposed. Its objective is to follow fast variations in input signals with reduced overshoot and settling time without deteriorating the steady-state performance of the buck regulator. The proposed approach enables fast system response through the BBTPE and an accurate steady-state output response through a low switching ripple and power efficient dynamic buck regulator. Fast output response with the help of the added module induces a slower rise of inductor current in the buck converter that further assists the proposed system to reduce both overshoot and settling time. To demonstrate the feasibility of the proposed solution, extensive simulations and experimental results from a discrete system are reported. The proposed supply modulator shows 80% improvement in rise time along with 60% reduction in both overshoot and settling time compared to the conventional dynamic buck regulator-based solution. Experimental results for a PA using the LTE 16-QAM 5 MHz standard shows improvement of 7.68 dB and 65.1% in ACPR and EVM, respectively. In a polar power amplifier, the input signal splits into phase and amplitude components using a non-linear conversion operation. This operation broadens the spectrum of the polar signal components. The information of amplitude and phase contains spectral images due to the sampling operation in non-linear conversion operation. These spectral images can be large and cause out-of-band emission in the output spectrum. In addition, during the recombination process of phase and amplitude, a delay mismatch between amplitude and phase signals, which can occur due to separate processing paths of amplitude and phase signals, causes out-of-band emissions, also known as spectral regrowth. This dissertation presents solutions to both of the issues of digital polar power amplifier: spectral images and delay mismatch. In order to reduce the problem of spectral images, interpolation of phase and amplitude is proposed in this work. This increases the effective sampling frequency of the amplitude and phase, which helps to improve the linearity by around 10 dB. In addition, a novel calibration scheme is proposed here for the delay mismatch between phase and amplitude path in a digital polar power amplifier. The scheme significantly reduces the spectral regrowth. The scheme uses the same path for phase and amplitude delay calculation after the recombination that allows having a robust calibration. Furthermore, it can be executed during the empty transmission slots. The proposed scheme is designed in a 40 nm CMOS technology and simulated with a 64-QAM IEEE 802.11n wireless standard. The scheme achieved 7.57 dB enhancement in ACLR and 84.35% improvement in EVM for a 3.5 ns mismatch in phase and amplitude path

An RF Carrier Bursting System using Partial Quantization Noise Cancellation

This paper introduces a novel method for bandpass cancellation of the quantization noise occurring in high efficiency, envelope pulsed transmitter architectures - or carrier bursting. An equivalent complex baseband model of the proposed system, including the Sigma Delta-modulator and cancellation signal generation, is developed. Analysis of the baseband model is performed, leading to analytical expressions of the power amplifier drain efficiency, assuming the use of an ideal class B power amplifier. These expressions are further used to study the impact of key system parameters, i.e. the compensation signal variance and clipping probability, on the class~B power amplifier drain efficiency and signal-to-noise ratio. The paper concludes with simulations followed by practical measurements in order to validate the functionality of the method and to evaluate the performance-trend predictions made by the theoretical framework in terms of efficiency and spectral purity

CMOS Integrated Power Amplifiers for RF Reconfigurable and Digital Transmitters

abstract: This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below: 1) A transformer-based power combiner architecture for out-phasing transmitters 2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA) 3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB. The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%. Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

RF Power Amplifier and Its Envelope Tracking

This dissertation introduces an agile supply modulator with optimal transient performance for the envelope tracking supply in linear power amplifiers. For this purpose, an on-demand current source module, the bang-bang transient performance enhancer (BBTPE), is proposed. Its objective is to follow fast variations in input signals with reduced overshoot and settling time without deteriorating the steady-state performance of the buck regulator. The proposed approach enables fast system response through the BBTPE and an accurate steady-state output response through a low switching ripple and power efficient dynamic buck regulator. Fast output response with the help of the added module induces a slower rise of inductor current in the buck converter that further assists the proposed system to reduce both overshoot and settling time. To demonstrate the feasibility of the proposed solution, extensive simulations and experimental results from a discrete system are reported. The proposed supply modulator shows 80% improvement in rise time along with 60% reduction in both overshoot and settling time compared to the conventional dynamic buck regulator-based solution. Experimental results for a PA using the LTE 16-QAM 5 MHz standard shows improvement of 7.68 dB and 65.1% in ACPR and EVM, respectively. In a polar power amplifier, the input signal splits into phase and amplitude components using a non-linear conversion operation. This operation broadens the spectrum of the polar signal components. The information of amplitude and phase contains spectral images due to the sampling operation in non-linear conversion operation. These spectral images can be large and cause out-of-band emission in the output spectrum. In addition, during the recombination process of phase and amplitude, a delay mismatch between amplitude and phase signals, which can occur due to separate processing paths of amplitude and phase signals, causes out-of-band emissions, also known as spectral regrowth. This dissertation presents solutions to both of the issues of digital polar power amplifier: spectral images and delay mismatch. In order to reduce the problem of spectral images, interpolation of phase and amplitude is proposed in this work. This increases the effective sampling frequency of the amplitude and phase, which helps to improve the linearity by around 10 dB. In addition, a novel calibration scheme is proposed here for the delay mismatch between phase and amplitude path in a digital polar power amplifier. The scheme significantly reduces the spectral regrowth. The scheme uses the same path for phase and amplitude delay calculation after the recombination that allows having a robust calibration. Furthermore, it can be executed during the empty transmission slots. The proposed scheme is designed in a 40 nm CMOS technology and simulated with a 64-QAM IEEE 802.11n wireless standard. The scheme achieved 7.57 dB enhancement in ACLR and 84.35% improvement in EVM for a 3.5 ns mismatch in phase and amplitude path

Design and Characterization of Power Converters and Amplifiers for Supply-Modulation based Transmitter Architectures

The rapid evolution of telecommunication systems has strongly influenced our lives, and the way we communicate and exchange information. Nevertheless, much progress is expected to happen in the next years with the introduction of new generations of wireless communications standards, which require signals with large bandwidth and very high Peak-to-Average Power Ratio (PAPR) in order to enhance the spectral efficiency and maximize the data rate. However, such developments can only take place through the evolution of Radio-Frequency (RF) which should be capable of working at higher frequencies, higher bandwidth and with higher efficiencies than before. In order to meet these demanding specifications, transmitter architectures have to evolve from a single linear RF Power-Amplifier (PA) into more complex architectures. Envelope Tracking (ET) is one of the most promising solutions for the efficiency-enhancement of next generation transmitters. The research described in this thesis aims to provide solutions to enhance the efficiency of the RF PA by means of an ET architecture. To this purpose, a novel discrete level supply modulator is investigated, which is based on a direct digital-to-analog power conversion. This supply modulator is capable of synthesizing eight voltage steps by means of three isolated voltage sources, thus behaving like a Power Digital-to-Analog Converter (Power-DAC). A hybrid version of the Power-DAC exploiting very fast GaN devices is developed and tested with an L-band PA achieving efficiency improvement up to 13% with 10 MHz of bandwidth. Furthermore, a monolithic GaN version of the Power-DAC is prototyped and tested with an X-band PA achieving efficiency improvement up to 20% and bandwidth of 20 MHz. This supply modulator is tested with outphasing PAs showing promising results with modulated signals and efficiency improvement up to 9%. Finally, dispersive phenomena, which affect PAs and switches in supply modulators, are investigated, characterized and modeled

High Efficiency Microwave Amplifiers and SiC Varactors Optimized for Dynamic Load Modulation

The increasing use of mobile networks as the main source of internet connectivity is creating challenges in the infrastructure. Customer demand is a moving target and continuous hardware developments are necessary to supply higher data rates in an environmentally sustainable and cost effective way. This thesis reviews and advances the status of realizing wideband and high efficiency power amplifiers, which will facilitate improvements in network capacity and energy efficiency. Several demonstrator PAs are proposed, analyzed, designed, and characterized: First, resistive loading at higher harmonics in wideband power amplifier design suitable for envelope tracking (ET) is proposed. A 40 dBm decade bandwidth 0.4–4.1 GHz PA is designed, with 10–15 dB gain and 40–62% drain efficiency. Its versatility is demonstrated by digital pre-distortion (DPD) linearized measurements resulting in adjacent channel leakage ratios (ACLR) lower than −46 dBc for various downlink signals (WCDMA, LTE, WiMAX). Second, a theory for class-J microwave frequency dynamic load modulation (DLM) PAs is derived. This connects transistor technology and load network requirements to enable power-scalable and bandwidth conscious designs. A 38 dBm PA is designed at 2.08 GHz, maintaining efficiencies >45% over 8 dB of output power back-off (OPBO) dynamic range. From this pre-study a fully packaged 86-W peak power version at 2.14 GHz is designed. ACLR after DPD is −46 dBc at a drain efficiency of 34%. For DLM PAs there is a need for varactors with large effective tuning range and high breakdown voltage. For this purpose, SiC Schottky diode varactors are developed with an effective tuning range of 6:1 and supporting a 3:1 tuning ratio at 36 V of RF swing. Nonlinear characterization to enable Q-factor extraction in the presence of distortion is proposed and demonstrated by multi-harmonic active source- and load-pull, offering insights to tunable network design. Third, a method to evaluate and optimize dual-RF input PAs, while catering to higher harmonic conditions and transistor parasitics, is proposed. The method is validated by a PA design having a peak power of 44 +/- 0.9 dBm and 6 dB OPBO PAE exceeding 45% over a 1–3 GHz bandwidth. The results in this thesis contribute with a novel device and analysis of high efficiency and wideband PAs, aiding in the design of key components for future energy efficient and high capacity wireless systems

Dynamic Load Modulation Scheme for Digital Transmitters

Nesta dissertação é proposto o dimensionamento de uma rede dinâmica de carga utilizando o algoritmo Particle Swam Optimization. A rede resultante deverá apresentar três níveis de impedância diferentes (10 Ohm, 20 Ohm e 30 Ohm), a mesma fase da corrente na antena, e uma eficiência intrínseca elevada. Os resultados preliminares foram testados e validados utilizando o ambiente de simulação Cadence Virtuoso com modelos BSIM, numa fase posterior os resultados são validados experimentalmente.The design of a Dynamic matching network topology, using the Particle Swarm Optimization (PSO) method is proposed in this dissertation. The resulting matching network should have three distinct impedance values (10Ohm 20Ohm and 30Ohm, the same current phase in the antenna and an high intrinsic efficiency. Preliminary results were tested and validated on the Cadence Virtuoso simulator with BSIM models and in a latter stage also real verification is performed

Power and radiofrequency hardware solutions for next generation sustainable communication systems and derived applications

RESUMEN: En la actualidad, en el área de las comunicaciones inalámbricas, existe una especial preocupación por reducir las emisiones de gases de efecto invernadero a la atmósfera y, por ende, el gasto energético. En este sentido, la eficiencia energética en las estaciones base (Radio Base Stations, RBS) juega un papel fundamental en los sistemas inalámbricos de comunicación. Los últimos avances hacia nuevas generaciones en las comunicaciones inalámbricas, empleando formatos de modulación espectralmente cada vez más eficientes, requieren manejar señales que presentan valores de relación de potencia pico a potencia promedio (PAPR) muy elevados. Por este motivo, el diseño de arquitecturas de transmisión para el 5G y los futuros estándares de comunicaciones inalámbricas es cada vez más complejo ya que se debe proporcionar una operación altamente eficiente sobre un rango de control de potencia de salida mayor. En este sentido, en esta tesis doctoral se proponen diferentes topologías inversoras de elevado rendimiento, operando en clase-E o basándose en la continuidad de modos de la clase-E, para su posterior utilización en transmisores eficientes de señales de comunicación. Se han diseñado e implementado amplificadores de potencia de bajas pérdidas y con reducida sensibilidad a las variaciones de la resistencia de carga que, al ser empleados en arquitecturas de transmisión, permiten manejar señales con altos valores de PAPR manteniendo una alta eficiencia y linealidad. De hecho, tras ser integrados en transmisores outphasing y en arquitecturas combinadas del tipo “Load Modulated Balanced Amplifiers (LMBA)” se han alcanzado valores de eficiencia que podrían considerarse en el estado del arte. Por otro lado, estas topologías amplificadoras también han sido utilizadas para diseñar e implementar su circuito dual con inversión temporal, el rectificador síncrono. Su implementación conjunta, al conectarlos en cascada, ha permitido el diseño e implementación de convertidores resonantes DC/DC, que podrían ser utilizados como moduladores de envolvente en arquitecturas Envelope Tracking (ET) y de Envelope Elimination and Restoration (EER), siendo también adecuados para su uso en fuentes de alimentación que requieran una alta densidad de potencia y una respuesta muy rápida, gracias a su reducido tamaño y elevado ancho de banda.ABSTRACT: Nowadays, in the area of wireless communications, there is a special concern to reduce greenhouse gas emissions into the atmosphere and, therefore, energy consumption. In this sense, energy efficiency in Radio Base Stations (RBS) plays a fundamental role in wireless communication systems. The latest advances towards new generations in wireless communications, employing increasingly efficient spectral modulation formats, require handling signals with very high peak to average power ratio (PAPR) values. For this reason, the design of transmission architectures for 5G and future wireless communication standards is increasingly complex since highly efficient operation must be provided over a wider output power control range. In this sense, this doctoral thesis proposes different high-efficiency topologies, operating in class-E or based on the continuity of class-E modes, for their use in efficient transmitters. Low loss power amplifiers with reduced sensitivity to load resistance variations have been designed and implemented that, when used in transmission architectures, allow handling signals with high PAPR values while maintaining a high efficiency and linearity. In fact, after being integrated in outphasing and Load Modulated Balanced Amplifier (LMBA) architectures, have been reached efficiency values that could be considered in the state of the art. On the other hand, these inverters have been used to design and implement their time reversal duality circuit, the synchronous rectifier. Their connection in cascade has allowed the design of resonant DC / DC converters, which could be used as envelope modulators in Envelope Tracking (ET) and Envelope Elimination and Restoration (EER) architectures, among others.Esta Tesis Doctoral ha sido generada directamente de la actividad científica desarrollada en los proyectos TEC2008-06684-C03-01, TEC2011-29126-C03-01 y TEC2014-58341-C4-1-R financiados por el MINECO y Fondos FEDER

Arquiteturas paralelas avançadas para transmissores 5G totalmente digitais

The fifth generation of mobile communications (5G) is being prepared and should be rolled out in the early coming years. Massive number of Radio-Frequency (RF) front-ends, peak data rates of 10 Gbps (everywhere and everytime), latencies lower than 10 msec and huge device densities are some of the expected disruptive capabilities. At the same time, previous generations can not be jeopardized, fostering the design of novel flexible and highly integrated radio transceivers able to support the simultaneous transmission of multi-band and multi-standard signals. The concept of all-digital transmission is being pointed out as a promising architecture to cope with such challenging requirements, due to its fully digital radio datapath. This thesis is focused on the proposal and validation of fully integrated and advanced digital transmitter architectures that excel the state-of-the-art in different figures of merit, such as transmission bandwidth, spectral purity, carrier agility, flexibility, and multi-band capability. The first part of this thesis introduces the concept of all-digital RF transmission. In particular, the foundations inherent to this thematic line are given, together with the recent advances reported in the state-of-the-art architectures.The core of this thesis, containing the main developments achieved during the Ph.D. work, is then presented and discussed. The first key contribution to the state-of-the-art is the use of cascaded Delta-Sigma (∆Σ) architectures to relax the analog filtering requirements of the conventional All-Digital Transmitters while maintaining the constant envelope waveform. Then, it is presented the first reported architecture where Antenna Arrays are directly driven by single-chip and single-bit All-Digital Transmitters, with promising results in terms of simplification of the RF front-ends and overall flexibility. Subsequently, the thesis proposes the first reported RF-stage All-Digital Transmitter that can be embedded within a single Field-Programmable Gate Array (FPGA) device. Thereupon, novel techniques to enable the design of wideband All-Digital Transmitters are reported. Finally, the design of concurrent multi-band transmitters is introduced. In particular, the design of agile and flexible dual and triple bands All-DigitalTransmitter (ADT) is demonstrated, which is a very important topic for scenarios that demand carrier aggregation. This Ph.D. contributes withseveral advances to the state-of-the-art of RF all-digital transmitters.A quinta geração de comunicações móveis (5G) está a ser preparada e deve ser comercializada nos próximos anos. Algumas das caracterı́sticas inovadoras esperadas passam pelo uso de um número massivo de font-ends de Rádio-Frequência (RF), taxas de pico de transmissão de dados de 10 Gbps (em todos os lugares e em todas as ocasiões), latências inferiores a 10 mseg e elevadas densidades de dispositivos. Ao mesmo tempo, as gerações anteriores não podem ser ignoradas, fomentando o design de novos transceptores de rádio flexı́veis e altamente integrados, capazes de suportar a transmissão simultânea de sinais multi-banda e multi-standard. O conceito de transmissão totalmente digital é considerado como um tipo de arquitetura promissora para lidar com esses requisitos desafiantes, devido ao seu datapath de rádio totalmente digital. Esta tese é focada na proposta e validação de arquiteturas de transmissores digitais totalmente integradas e avançadas que ultrapassam o estado da arte em diferentes figuras de mérito, como largura de banda de transmissão, pureza espectral, agilidade de portadora, flexibilidade e capacidade multibanda. A primeira parte desta tese introduz o conceito de transmissores de RF totalmente digitais. Em particular, os fundamentos inerentes a esta linha temática são apresentados, juntamente com os avanços mais recentes do estado-da-arte. O núcleo desta tese, contendo os principais desenvolvimentos alcançados durante o trabalho de doutoramento, é então apresentado e discutido. A primeira contribuição fundamental para o estado da arte é o uso de arquiteturas em cascata com moduladores ∆Σ para relaxar os requisitos de filtragem analógica dos transmissores RF totalmente digitais convencionais, mantendo a forma de onda envolvente constante. Em seguida, é apresentada a primeira arquitetura em que agregados de antenas são excitados diretamente por transmissores digitais de um único bit inseridos num único chip, com resultados promissores em termos de simplificação dos front-ends de RF e flexibilidade em geral. Posteriormente, é proposto o primeiro transmissor totalmente digital RF-stage relatado que pode ser incorporado dentro de um único Agregado de Células Lógicas Programáveis. Novas técnicas para permitir o desenho de transmissores RF totalmente digitais de banda larga são também apresentadas. Finalmente, o desenho de transmissores simultâneos de múltiplas bandas é exposto. Em particular, é demonstrado o desenho de transmissores de duas e três bandas ágeis e flexı́veis, que é um tópico essencial para cenários que exigem agregação de múltiplas bandas.Apoio financeiro da Fundação para a Ciência e Tecnologia (FCT) no âmbito de uma bolsa de doutoramento, ref. PD/BD/105857/2014.Programa Doutoral em Telecomunicaçõe