12 research outputs found
OSCILLATION-BASED TESTING METHOD FOR DETECTING SWITCH FAULTS IN HIGH-Q SC BIQUAD FILTERS
Testing switched capacitor circuits is a challenge due to the diversity of the possible faults. A special problem encountered is the synthesis of the test signal that will control and will make the fault-effect observable at the test point. The oscillation based method which was adopted for testing in these proceedings resolves that important issue by his nature. Here we discuss the properties of the method and the conditions to be fulfilled in order to implement it in the right way. To achieve that we resolved the problem of synthesis of the positive feed-back circuit and the choice of a proper model of the operational amplifier. In that way a realistic foundation to the testing process was generated. A second order notch cell was chosen as a case-study. Fault dictionaries were developed related to the catastrophic faults of the switches used within the cell. The results reported here are a continuation of our previous work and are complimentary to some other already published
On-line Testing Field Programmable Analog Array Circuits
This work presents an efficient methodology to on-line test field programmable analog array (FPAA) circuits. It proposes to partition the FPAA circuit under test into sub circuits. Each sub circuit is tested by replicating the sub circuit with programmable resources on FPAAs, and comparing the outputs of the original partitioned sub circuit and its replication. The advantages of this approach includes: low implementation cost, enhanced testability, and flexible testing schedules. This work also presents circuit techniques to address stability problems which are often encountered in the proposed on-line testing approach. In addition, the impact of performing circuit partition on testability is investigated in this work. It shows that testability is generally improved in partitioned circuits. Finally, experimental results are presented to demonstrate the feasibility and effectiveness of the proposed techniques
On-Chip Analog Circuit Design Using Built-In Self-Test and an Integrated Multi-Dimensional Optimization Platform
Nowadays, the rapid development of system-on-chip (SoC) market introduces
tremendous complexity into the integrated circuit (IC) design. Meanwhile, the IC
fabrication process is scaling down to allow higher density of integration but makes
the chips more sensitive to the process-voltage-temperature (PVT) variations. A
successful IC product not only imposes great pressure on the IC designers, who have
to handle wider variations and enforce more design margins, but also challenges the
test procedure, leading to more check points and longer test time. To relax the
designers’ burden and reduce the cost of testing, it is valuable to make the IC chips
able to test and tune itself to some extent.
In this dissertation, a fully integrated in-situ design validation and optimization
(VO) hardware for analog circuits is proposed. It implements in-situ built-in self-test
(BIST) techniques for analog circuits. Based on the data collected from BIST,
the error between the measured and the desired performance of the target circuit is
evaluated using a cost function. A digital multi-dimensional optimization engine is
implemented to adaptively adjust the analog circuit parameters, seeking the minimum
value of the cost function and achieving the desired performance. To verify
this concept, study cases of a 2nd/4th active-RC band-pass filter (BPF) and a 2nd
order Gm-C BPF, as well as all BIST and optimization blocks, are adopted on-chip.
Apart from the VO system, several improved BIST techniques are also proposed
in this dissertation. A single-tone sinusoidal waveform generator based on a finite-impulse-response (FIR) architecture, which utilizes an optimization algorithm to
enhance its spur free dynamic range (SFDR), is proposed. It achieves an SFDR of
59 to 70 dBc from 150 to 850 MHz after the optimization procedure. A low-distortion
current-steering two-tone sinusoidal signal synthesizer based on a mixing-FIR architecture is also proposed. The two-tone synthesizer extends the FIR architecture to
two stages and implements an up-conversion mixer to generate the two tones, achieving better than -68 dBc IM3 below 480 MHz LO frequency without calibration.
Moreover, an on-chip RF receiver linearity BIST methodology for continuous and
discrete-time hybrid baseband chain is proposed. The proposed receiver chain
implements a charge-domain FIR filter to notch the two excitation signals but expose
the third order intermodulation (IM3) tones. It simplifies the linearity measurement
procedure–using a power detector is enough to analyze the receiver’s linearity.
Finally, a low cost fully digital built-in analog tester for linear-time-invariant
(LTI) analog blocks is proposed. It adopts a time-to-digital converter (TDC) to
measure the delays corresponded to a ramp excitation signal and is able to estimate
the pole or zero locations of a low-pass LTI system
Symbolic tolerance and sensitivity analysis of large scale electronic circuits
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