Reliability-aware and energy-efficient system level design for networks-on-chip

2015 Spring.Includes bibliographical references.With CMOS technology aggressively scaling into the ultra-deep sub-micron (UDSM) regime and application complexity growing rapidly in recent years, processors today are being driven to integrate multiple cores on a chip. Such chip multiprocessor (CMP) architectures offer unprecedented levels of computing performance for highly parallel emerging applications in the era of digital convergence. However, a major challenge facing the designers of these emerging multicore architectures is the increased likelihood of failure due to the rise in transient, permanent, and intermittent faults caused by a variety of factors that are becoming more and more prevalent with technology scaling. On-chip interconnect architectures are particularly susceptible to faults that can corrupt transmitted data or prevent it from reaching its destination. Reliability concerns in UDSM nodes have in part contributed to the shift from traditional bus-based communication fabrics to network-on-chip (NoC) architectures that provide better scalability, performance, and utilization than buses. In this thesis, to overcome potential faults in NoCs, my research began by exploring fault-tolerant routing algorithms. Under the constraint of deadlock freedom, we make use of the inherent redundancy in NoCs due to multiple paths between packet sources and sinks and propose different fault-tolerant routing schemes to achieve much better fault tolerance capabilities than possible with traditional routing schemes. The proposed schemes also use replication opportunistically to optimize the balance between energy overhead and arrival rate. As 3D integrated circuit (3D-IC) technology with wafer-to-wafer bonding has been recently proposed as a promising candidate for future CMPs, we also propose a fault-tolerant routing scheme for 3D NoCs which outperforms the existing popular routing schemes in terms of energy consumption, performance and reliability. To quantify reliability and provide different levels of intelligent protection, for the first time, we propose the network vulnerability factor (NVF) metric to characterize the vulnerability of NoC components to faults. NVF determines the probabilities that faults in NoC components manifest as errors in the final program output of the CMP system. With NVF aware partial protection for NoC components, almost 50% energy cost can be saved compared to the traditional approach of comprehensively protecting all NoC components. Lastly, we focus on the problem of fault-tolerant NoC design, that involves many NP-hard sub-problems such as core mapping, fault-tolerant routing, and fault-tolerant router configuration. We propose a novel design-time (RESYN) and a hybrid design and runtime (HEFT) synthesis framework to trade-off energy consumption and reliability in the NoC fabric at the system level for CMPs. Together, our research in fault-tolerant NoC routing, reliability modeling, and reliability aware NoC synthesis substantially enhances NoC reliability and energy-efficiency beyond what is possible with traditional approaches and state-of-the-art strategies from prior work

Delay Tolerant Networks for Efficient Information Harvesting and Distribution in Intelligent Transportation Systems

[EN] Intelligent Transportation Systems (ITS) can make transportation safer, more efficient, and more sustainable by applying various information and communication technologies. One of these technologies are \acfp{VN}. \acp{VN} combine different communication solutions such as cellular networks, \acfp{VANET}, or IEEE 802.11 technologies to provide connectivity among vehicles, and between vehicles and road infrastructure. This thesis focuses on VNs, and considers that the high speed of the nodes and the presence of obstacles like buildings, produces a highly variable network topology, as well as more frequent partitions in the network. Therefore, classical \ac{MANET} protocols do not adapt well to VANETs. Under these conditions, \ac{DTN} have been proposed as an alternative able to cope with these adverse characteristics. In DTN, when a message cannot be routed to its destination, it is not immediately dropped but it is instead stored and carried until a new route becomes available. The combination of VN and DTN is called \acp{VDTN}. In this thesis, we propose a new VDTN protocol designed to collect information from vehicular sensors. Our proposal, called \ac{MSDP}, combines information about the localization obtained from a GNSS system with the actual street/road layout obtained from a Navigation System (NS) to define a new routing metric. Both analytical and simulation results prove that MSDP outperforms previous proposals. Concerning the deployment of VNs and VANET technologies, technology already left behind the innovation and the standardization phases, and it is about time it reach the first early adopters in the market. However, most car manufacturers have decided to implement VN devices in the form of On Board Units (OBUs), which are expensive, heavily manufacturer dependent, and difficult to upgrade. These facts are delaying the deployment of VN. To boost this process, we have developed the GRCBox architecture. This architecture is based on low-cost devices and enables the establishment of V2X, \emph{i.e.} V2I and V2V, communications while integrating users by easing the use of general purpose devices like smartphones, tablets or laptops. To demonstrate the viability of the GRCBox architecture, we combined it with a DTN platform called Scampi to obtain actual results over a real VDTN scenario. We also present several GRCBox-aware applications that illustrate how developers can create applications that bring the potential of VN to user devices.[ES] Los sistemas de transporte inteligente (ITS) son el soporte para el establecimiento de un transporte más seguro, más eficiente y más sostenible mediante el uso de tecnologías de la información y las comunicaciones. Una de estas tecnologías son las redes vehiculares (VNs). Las VNs combinan diferentes tecnologías de comunicación como las redes celulares, las redes ad-hoc vehiculares (VANETs) o las redes 802.11p para proporcionar conectividad entre vehículos, y entre vehículos y la infraestructura de carreteras. Esta tesis se centra en las VNs, en las cuales la alta velocidad de los nodos y la presencia de obstáculos como edificios producen una topología de red altamente variable, así como frecuentes particiones en la red. Debido a estas características, los protocolos para redes móviles ad-hoc (MANETs) no se adaptan bien a las VANETs. En estas condiciones, las redes tolerantes a retardos (DTNs) se han propuesto como una alternativa capaz de hacer frente a estos problemas. En DTN, cuando un mensaje no puede ser encaminado hacia su destino, no es inmediatamente descartado sino es almacenado hasta que una nueva ruta esta disponible. Cuando las VNs y las DTNs se combinan surgen las redes vehiculares tolerantes a retardos (VDTN). En esta tesis proponemos un nuevo protocolo para VDTNs diseñado para recolectar la información generada por sensores vehiculares. Nuestra propuesta, llamada MSDP, combina la información obtenida del servicio de información geográfica (GIS) con el mapa real de las calles obtenido del sistema de navegación (NS) para definir una nueva métrica de encaminamiento. Resultados analíticos y mediante simulaciones prueban que MSDP mejora el rendimiento de propuestas anteriores. En relación con el despliegue de las VNs y las tecnologías VANET, la tecnología ha dejado atrás las fases de innovación y estandarización, ahora es el momento de alcanzar a los primeros usuarios del mercado. Sin embargo, la mayoría de fabricantes han decidido implementar los dispositivos para VN como unidades de a bordo (OBU), las cuales son caras y difíciles de actualizar. Además, las OBUs son muy dependientes del fabricante original. Todo esto esta retrasando el despliegue de las VNs. Para acelerar la adopción de las VNs, hemos desarrollado la arquitectura GRCBox. La arquitectura GRCBox esta basada en un dispositivo de bajo coste que permite a los usuarios usar comunicaciones V2X (V2V y V2I) mientras utilizan dispositivos de propósito general como teléfonos inteligentes, tabletas o portátiles. Las pruebas incluidas en esta tesis demuestran la viabilidad de la arquitectura GRCBox. Mediante la combinación de nuestra GRCBox y una plataforma de DTN llamada Scampi hemos diseñado y probado un escenario VDTN real. También presentamos como los desarrolladores pueden crear nuevas aplicaciones GRCBox para llevar el potencial de las VN a los dispositivos de usuario.[CA] Els sistemes de transport intel·ligent (ITS) poden crear un transport més segur, més eficient i més sostenible mitjançant l'ús de tecnologies de la informació i les comunicacions aplicades al transport. Una d'aquestes tecnologies són les xarxes vehiculars (VN). Les VN combinen diferents tecnologies de comunicació, com ara les xarxes cel·lulars, les xarxes ad-hoc vehiculars (VANET) o les xarxes 802.11p, per a proporcionar comunicació entre vehicles, i entre vehicles i la infraestructura de carreteres. Aquesta tesi se centra en les VANET, en les quals l'alta velocitat dels nodes i la presència d'obstacles, com els edificis, produeixen una topologia de xarxa altament variable, i també freqüents particions en la xarxa. Per aquest motiu, els protocols per a xarxes mòbils ad-hoc (MANET) no s'adapten bé. En aquestes condicions, les xarxes tolerants a retards (DTN) s'han proposat com una alternativa capaç de fer front a aquests problemes. En DTN, quan un missatge no pot ser encaminat cap a la seua destinació, no és immediatament descartat sinó que és emmagatzemat fins que apareix una ruta nova. Quan les VN i les DTN es combinen sorgeixen les xarxes vehicular tolerants a retards (VDTN). En aquesta tesi proposem un nou protocol per a VDTN dissenyat per a recol·lectar la informació generada per sensors vehiculars. La nostra proposta, anomenada MSDP, combina la informació obtinguda del servei d'informació geogràfica (GIS) amb el mapa real dels carrers obtingut del sistema de navegació (NS) per a definir una nova mètrica d'encaminament. Resultats analítics i mitjançant simulacions proven que MSDP millora el rendiment de propostes prèvies. En relació amb el desplegament de les VN i les tecnologies VANET, la tecnologia ha deixat arrere les fases d'innovació i estandardització, ara és temps d'aconseguir als primers usuaris del mercat. No obstant això, la majoria de fabricants han decidit implementar els dispositius per a VN com a unitats de bord (OBU), les quals són cares i difícils d'actualitzar. A més, les OBU són molt dependents del fabricant original. Tot això està retardant el desplegament de les VN. Per a accelerar l'adopció de les VN, hem desenvolupat l'arquitectura GRCBox. L'arquitectura GRCBox està basada en un dispositiu de baix cost que permet als usuaris usar comunicacions V2V mentre usen dispositius de propòsit general, com ara telèfons intel·ligents, tauletes o portàtils. Les proves incloses en aquesta tesi demostren la viabilitat de l'arquitectura GRCBox. Mitjançant la combinació de la nostra GRCBox i la plataforma de DTN Scampi, hem dissenyat i provat un escenari VDTN pràctic. També presentem com els desenvolupadors poden crear noves aplicacions GRCBox per a portar el potencial de les VN als dispositius d'usuari.Martínez Tornell, S. (2016). Delay Tolerant Networks for Efficient Information Harvesting and Distribution in Intelligent Transportation Systems [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/68486TESI

Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chip

Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 52%--81% inaccuracy. We propose an accurate circuit-level fault-modeling tool, which can be plugged into any system-level NoC simulator, quantify the system-level impact of PV-induced faults at runtime, pinpoint fault-prone router components that should be protected, and accurately evaluate alternative resilient multi-core designs.GigaScale Systems Research CenterFocus Center Research Program. Focus Center for Circuit & System Solutions. Semiconductor Research Corporation. Interconnect Focus Cente

Doctor of Philosophy

dissertationPortable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are under a demand to offer more functionality and increased battery life. A difficult problem in SoC design is providing energy-efficient communication between its components while maintaining the required performance. This dissertation introduces a novel energy-efficient network-on-chip (NoC) communication architecture. A NoC is used within complex SoCs due it its superior performance, energy usage, modularity, and scalability over traditional bus and point-to-point methods of connecting SoC components. This is the first academic research that combines asynchronous NoC circuits, a focus on energy-efficient design, and a software framework to customize a NoC for a particular SoC. Its key contribution is demonstrating that a simple, asynchronous NoC concept is a good match for low-power devices, and is a fruitful area for additional investigation. The proposed NoC is energy-efficient in several ways: simple switch and arbitration logic, low port radix, latch-based router buffering, a topology with the minimum number of 3-port routers, and the asynchronous advantages of zero dynamic power consumption while idle and the lack of a clock tree. The tool framework developed for this work uses novel methods to optimize the topology and router oorplan based on simulated annealing and force-directed movement. It studies link pipelining techniques that yield improved throughput in an energy-efficient manner. A simulator is automatically generated for each customized NoC, and its traffic generators use a self-similar message distribution, as opposed to Poisson, to better match application behavior. Compared to a conventional synchronous NoC, this design is superior by achieving comparable message latency with half the energy