Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

Decoherence of Flux Qubits Coupled to Electronic Circuits

On the way to solid-state quantum computing, overcoming decoherence is the central issue. In this contribution, we discuss the modeling of decoherence of a superonducting flux qubit coupled to dissipative electronic circuitry. We discuss its impact on single qubit decoherence rates and on the performance of two-qubit gates. These results can be used for designing decoherence-optimal setups.Comment: 16 pages, 5 figures, to appear in Advances in Solid State Physics, Vol. 43 (2003

Delay-time optimization for driving and sensing of signals on high-capacitance paths of VLSI systems

Minimization of the delay times associated with driving and sensing signals from large capacitance paths by optimizing the fan-out factor of the driver stages, the gain of the input sensing stages, and the path voltage swing are examined. Examples of driving signals on a high capacitance path with two driving schemes are: a push-pull depletion-load driver chain and a fixed driver; and of sensing signals with two sensing schemes: a single-ended depletion-load inverter input stage and a balanced regenerative strobed latch are presented

The Fastest Mixing Markov Process on a Graph and a Connection to a Maximum Variance Unfolding Problem

We consider a Markov process on a connected graph, with edges labeled with transition rates between the adjacent vertices. The distribution of the Markov process converges to the uniform distribution at a rate determined by the second smallest eigenvalue lambda_2 of the Laplacian of the weighted graph. In this paper we consider the problem of assigning transition rates to the edges so as to maximize lambda_2 subject to a linear constraint on the rates. This is the problem of finding the fastest mixing Markov process (FMMP) on the graph. We show that the FMMP problem is a convex optimization problem, which can in turn be expressed as a semidefinite program, and therefore effectively solved numerically. We formulate a dual of the FMMP problem and show that it has a natural geometric interpretation as a maximum variance unfolding (MVU) problem, , the problem of choosing a set of points to be as far apart as possible, measured by their variance, while respecting local distance constraints. This MVU problem is closely related to a problem recently proposed by Weinberger and Saul as a method for "unfolding" high-dimensional data that lies on a low-dimensional manifold. The duality between the FMMP and MVU problems sheds light on both problems, and allows us to characterize and, in some cases, find optimal solutions

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

High-bandwidth uni-traveling carrier waveguide photodetector on an InP-membrane-on-silicon platform

A uni-traveling carrier photodetector (UTC-PD), heterogeneously integrated on silicon, is demonstrated. It is fabricated in an InP-based photonic membrane bonded on a silicon wafer, using a novel double-sided processing scheme. A very high 3 dB bandwidth of beyond 67 GHz is obtained, together with a responsivity of 0.7 A/W at 1.55 μm wavelength. In addition, open eye diagrams at 54 Gb/s are observed. These results promise high speed applications using a novel full-functionality photonic platform on silicon