Transistor-Level Layout of Integrated Circuits

In this dissertation, we present the toolchain BonnCell and its underlying algorithms. It has been developed in close cooperation with the IBM Corporation and automatically generates the geometry for functional groups of 2 to approximately 50 transistors. Its input consists of a set of transistors, including properties like their sizes and their types, a specification of their connectivity, and parameters to flexibly control the technological framework as well as the algorithms' behavior. Using this data, the tool computes a detailed geometric realization of the circuit as polygonal shapes on 16 layers. To this end, a placement routine configures the transistors and arranges them in the plane, which is the main subject of this thesis. Subsequently, a routing engine determines wires connecting the transistors to ensure the circuit's desired functionality. We propose and analyze a family of algorithms that arranges sets of transistors in the plane such that a multi-criteria target function is optimized. The primary goal is to obtain solutions that are as compact as possible because chip area is a valuable resource in modern techologies. In addition to the core algorithms we formulate variants that handle particularly structured instances in a suitable way. We will show that for 90% of the instances in a representative test bed provided by IBM, BonnCell succeeds to generate fully functional layouts including the placement of the transistors and a routing of their interconnections. Moreover, BonnCell is in wide use within IBM's groups that are concerned with transistor-level layout - a task that has been performed manually before our automation was available. Beyond the processing of isolated test cases, two large-scale examples for applications of the tool in the industry will be presented: On the one hand the initial design phase of a large SRAM unit required only half of the expected 3 month period, on the other hand BonnCell could provide valuable input aiding central decisions in the early concept phase of the new 14 nm technology generation

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Methods and tools for the design of RFICs

Ambient intelligence is going to focus the next advances in wireless technologies. Hence, the increasing demand on radio frequency (RF) devices and applications represents, not only a challenge for technological industries to improve its roadmaps, but also for RF engineers to design more robust, low-power, small-size and low-cost devices. Regarding to communication robustness, in the latest years, differential topologies have acquired an important relevance because of its natural noise and interference immunity. Within this framework, a differential n-port device can still be treated with the classical analysis circuit theory by means of Z-,Y-, h-parameters or the most suitable S-parameters in the radio frequency field. Despite of it, Bockelman introduced the mixed-mode scattering parameters, which more properly express the differential and common-mode behavior of symmetrical devices. Since then, such parameters have been used with a varying degree of success, as it will be shown, mainly because of a misinterpretation. Thereby, this thesis is devoted to extend the theory of mixed-mode scattering parameters and proposes the methodology to analyze such devices. For this proposal, the simplest case of a two-port device is developed. By solving this simple case, most of the lacks of the current theory are filled up. As instance, it allows the characterization and comparison of symmetric and spiral inductors, which have remained a controversy point until now. After solving this case, the theory is extended to a n-port device. Another key point on the fast and inexpensive development of radio frequency devices is the advance on fast CAD tools for the analysis and synthesis of passive devices. In the case of silicon technologies, planar inductors have become the most popular shapes because of its integrability. However, the design of inductors entails a deep experience and acknowledge not only on the behavior of such devices but on the use of electromagnetic (EM) simulators. Unfortunately, the use of EM simulators consumes an important quantity of time and resources. Thereby, this thesis is devoted to improve some of the aspects that slow down the synthesis process of inductors. Therefore, an ‘ab initio’ technique for the meshing of planar radio frequency and microwave circuits is described. The technique presented can evaluate the losses in the component with a high accuracy just in few seconds where an electromagnetic simulator would normally last hours. Likewise, a simple bisection algorithm for the synthesis of compact planar inductors is presented. It is based on a set of heuristic rules obtained from the study of the electromagnetic behavior of these planar devices. Additionally, design of a single-ended to differential low noise amplifier (LNA) in a CMOS technology is performed by using the methods and tools described.L'enginyeria de radiofreqüència i la tecnologia de microones han assolit un desenvolupament inimaginable i avui en dia formen part de la majoria de les nostres activitats diàries. Probablement, la tecnologia mòbil ha tingut un desenvolupament més ràpid que qualsevol altre avenç tecnològic de l'era digital. Avui en dia, podem dir que el paradigma de la mobilitat s'ha assolit i tenim accés ràpid a internet des de qualsevol lloc on podem estar amb un dispositiu de butxaca. No obstant això, encara hi ha fites per endavant. Es més que probable que el paradigma de l’ "ambient intelligence” sigui el centre dels pròxims avenços en les tecnologies sense fils. A diferencia del paradigma de l"ambient intelligence', l'evolució de la tecnologia de la informació mai ha tingut l'objectiu explícit de canviar la societat, sinó que ho van fer com un efecte secundari, en canvi, les visions d' “ambient intelligence” proposen expressament el transformar la societat mitjançant la connexió completa i la seva informatització. Per tant, l'augment de la demanda de dispositius de ràdio freqüència (RF) i de les seves possibles aplicacions representa, no només un repte per a les indústries tecnològiques per millorar els seus plans de treball, sinó també per als enginyers de RF que hauran de dissenyar dispositius de baixa potència, més robusts, de mida petita i de baix cost. Quant a la robustesa dels dispositius, en els últims anys, les topologies de tipus diferencial han adquirit una important rellevància per la seva immunitat natural al soroll i resistència a les interferències. Dins d'aquest marc, un dispositiu de nports diferencial, encara pot ser tractat com un dispositiu 2nx2n i la teoria clàssica d'anàlisi de circuits (és a dir, la temia de quadripols) es pot aplicar a través de paràmetres Z, Y, h o els paràmetres S, més adequats en el camp de freqüència de ràdio. Tot i això, Bockelman i Eisenstadt introdueixen els paràmetres S mixtos, que expressen més adequadament el comportament diferencial i en mode comú de dispositius simètrics o asimètrics. Des de llavors, aquests paràmetres s'han utilitzat amb un grau variable d'èxit, com es mostrarà, principalment a causa d'una mala interpretació. D'aquesta manera, la primera part d'aquesta tesi està dedicada a estendre la teoria dels paràmetres S de mode mixt i proposa la metodologia d'anàlisi d'aquest tipus de dispositius i circuits. D'aquesta forma, en el Capítol 2, es desenvolupa el cas més simple d'un dispositiu de dos ports. En resoldre aquest cas simple, la major part de les mancances de la teoria actual es posen de relleu. Com a exemple, pennet la caracterització i la comparació de bobines simètriques i espiral no simètriques, que han estat un punt de controvèrsia fins ara. Després de resoldre aquest cas, al Capítol 3 s'estén la teOIia a un dispositiu de n-ports dels quals un nombre pot ser single-ended i la resta diferencials. És en aquest moment quan la dualitat existent entre els paràmetres S estàndard i de mode mixt es pot veure clarament i es destaca en el seu conjunt. Aquesta teoria permet, tanmateix, estendre la teoria clàssica d'amplificadors quan s'analitzen per mitjà de paràmetres S. Un altre punt clau en el desenvolupament ràpid i de baix cost dels dispositius de radiofreqüència és l'avenç en les eines CAD ràpides per a l'anàlisi i síntesi dels dispositius passius, en especial dels inductors. Aquests dispositius apareixen tot sovint en el disseny de radio freqüència degut a la seva gran versatilitat. Tot i que hi ha hagut múltiples intents de reemplaçar amb components externs o circuits, fins i tot actius, en el cas de les tecnologies de silici, els inductors planars s'han convertit en les formes més populars per la seva integrabilitat. No obstant això, el disseny d'inductors implica conèixer i posseir una experiència profunda no només en el comportament d'aquests dispositius, però també en l'ús de simuladors electromagnètics (EM). Desafortunadament, l'ús dels simuladors EM consumeix una quantitat important de temps i recursos. Per tant, la síntesi dels inductors representa un important inconvenient actualment. D'aquesta manera, la segona part d'aquesta tesi està dedicada a millorar alguns dels aspectes que frenen el procés de síntesi dels inductors. Per tant, en el Capítol 4, es descriu una tècnica 'ab initio' de generació de la malla per bobines planars en ràdio freqüència i microones. La tècnica es basa en l'estudi analític dels fenòmens d'aglomeració de corrent que tenen lloc a l'interior del component. En aquesta avaluació, no es requereix una solució explícita dels corrents i de les càrregues arreu del circuit. Llavors, el nombre de cel•les de la malla assignades a una tira de metall donada, depèn del valor inicialment obtingut a partir de l'estudi analític. La tècnica presentada pot avaluar les pèrdues en el component amb una gran precisió només en uns pocs segons, quan comparat amb un simulador electromagnètic normalment es necessitaria hores. De la mateixa manera, en el Capítol 5 es presenta un senzill algoritme de bisecció per a la síntesi d'inductors planars compactes. Es basa en un conjunt de regles heurístiques obtingut a partir de l'estudi del comportament electromagnètic d'aquests dispositius planars. D'aquesta manera, el nombre d'iteracions es manté moderadament baix.D'altra banda, per tal d'accelerar l'anàlisi en cada pas, s'utilitza un simulador ràpid electromagnètic planar, el qual es basa en el coneixement que es té del component sintetitzat. Finalment, en el Capítol 6, la metodologia de paràmetres S de mode mixt proposada i les eines CAD introduides s'utilitzen àmpliament en el disseny d'un amplificador de baix soroll “single-ended” a diferencial (LNA), mitjançant una tecnologia estàndard CMOS.L'amplificador de baix soroll és un dels components claus en un sistema de recepció de radio freqüència, ja que tendeix a dominar la sensibilitat i la figura de soroll (NF) de tot el sistema. D'altra banda, les característiques d'aquest circuit estan directament relacionades amb els components actius i passius disponibles en una tecnologia donada. Per tant, la tecnologia escollida, el factor de qualitat dels passius, i la forma com es caracteritzen tindran un alt impacte en les principals figures de mèrit del circuit real

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Analog design for manufacturability: lithography-aware analog layout retargeting

As transistor sizes shrink over time in the advanced nanometer technologies, lithography effects have become a dominant contributor of integrated circuit (IC) yield degradation. Random manufacturing variations, such as photolithographic defect or spot defect, may cause fatal functional failures, while systematic process variations, such as dose fluctuation and defocus, can result in wafer pattern distortions and in turn ruin circuit performance. This dissertation is focused on yield optimization at the circuit design stage or so-called design for manufacturability (DFM) with respect to analog ICs, which has not yet been sufficiently addressed by traditional DFM solutions. On top of a graph-based analog layout retargeting framework, in this dissertation the photolithographic defects and lithography process variations are alleviated by geometrical layout manipulation operations including wire widening, wire shifting, process variation band (PV-band) shifting, and optical proximity correction (OPC). The ultimate objective of this research is to develop efficient algorithms and methodologies in order to achieve lithography-robust analog IC layout design without circuit performance degradation

The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

A framework for fine-grain synthesis optimization of operational amplifiers

This thesis presents a cell-level framework for Operational Amplifiers Synthesis (OASYN) coupling both circuit design and layout. For circuit design, the tool applies a corner-driven optimization, accounting for on-chip performance variations. By exploring the process, voltage, and temperature variations space, the tool extracts design worst case solution. The tool undergoes sensitivity analysis along with Pareto-optimality to achieve required specifications. For layout phase, OASYN generates a DRC proved automated layout based on a sized circuit-level description. Morata et al. (1996) introduced an elegant representation of block placement called sequence pair for general floorplans (SP). Like TCG and BSG, but unlike O-tree, B*tree, and CBL, SP is P-admissible. Unlike SP, TCG supports incremental update during operation and keeps the information of the boundary modules as well as their relative positions in the representation. Block placement algorithms that are based on SP use heuristic optimization algorithms, e.g., simulated annealing where generation of large number of sequence pairs are required. Therefore a fast algorithm is needed to generate sequence pairs after each solution perturbation. The thesis presents a new simple and efficient O(n) runtime algorithm for fast realization of incremental update for cost evaluation. The algorithm integrates sequence pair and transitive closure graph advantages into TCG-S* a superior topology update scheme which facilitates the search for optimum desired floorplan. Experiments show that TCG-S* is better than existing works in terms of area utilization and convergence speed. Routing-aware placement is implemented in OASYN, handling symmetry constraints, e.g., interdigitization, common centroid, along with congestion elimination and the enhancement of placement routability