Leveraging Signal Transfer Characteristics and Parasitics of Spintronic Circuits for Area and Energy-Optimized Hybrid Digital and Analog Arithmetic

While Internet of Things (IoT) sensors offer numerous benefits in diverse applications, they are limited by stringent constraints in energy, processing area and memory. These constraints are especially challenging within applications such as Compressive Sensing (CS) and Machine Learning (ML) via Deep Neural Networks (DNNs), which require dot product computations on large data sets. A solution to these challenges has been offered by the development of crossbar array architectures, enabled by recent advances in spintronic devices such as Magnetic Tunnel Junctions (MTJs). Crossbar arrays offer a compact, low-energy and in-memory approach to dot product computation in the analog domain by leveraging intrinsic signal-transfer characteristics of the embedded MTJ devices. The first phase of this dissertation research seeks to build on these benefits by optimizing resource allocation within spintronic crossbar arrays. A hardware approach to non-uniform CS is developed, which dynamically configures sampling rates by deriving necessary control signals using circuit parasitics. Next, an alternate approach to non-uniform CS based on adaptive quantization is developed, which reduces circuit area in addition to energy consumption. Adaptive quantization is then applied to DNNs by developing an architecture allowing for layer-wise quantization based on relative robustness levels. The second phase of this research focuses on extension of the analog computation paradigm by development of an operational amplifier-based arithmetic unit for generalized scalar operations. This approach allows for 95% area reduction in scalar multiplications, compared to the state-of-the-art digital alternative. Moreover, analog computation of enhanced activation functions allows for significant improvement in DNN accuracy, which can be harnessed through triple modular redundancy to yield 81.2% reduction in power at the cost of only 4% accuracy loss, compared to a larger network. Together these results substantiate promising approaches to several challenges facing the design of future IoT sensors within the targeted applications of CS and ML

Direct Laser Writing of Metal and Metal Oxide Patterns for Flexible and Memristive Electronic Components

Growing interest in the fields of flexible electronics and AI are leading the development of new manufacturing techniques able to make computer hardware devices that can suite their unique needs. Research into these areas is stalled by the high cost of manufacturing putting rapid and low-cost manufacturing methods in high demand. Direct Laser Writing, as a novel manufacturing technique, has been shown to be able to produce flexible electronic devices rapidly and with the use of inexpensive raw materials. It works by treating a substrate coated in a metal ion precursor with focused laser irradiation. Where the laser interacts with the precursor organic reduction agents within the precursor are able to reduce the metal ions which then form nanoparticles that are then sintered to form interconnected nanoparticle networks. In this work direct laser writing is utilized to develop a manufacturing technique of novel flexible electronics for neuromorphic computing hardware. Direct laser writing of copper and copper patterns is used to study the relationship between applied laser energy and electrical properties of deposited patterns. Other metals are also studied. Anodic metals are not able to be fully reduced and are deposited as metal oxides. Cathodic metals are easily reduced and deposited as metals. Metals with intermediate reduction potentials can selectively be deposited as either metals or metal oxides. Deposition of metal alloys with homogenous composition is also demonstrated through the deposition of copper-nickel alloys. Memristor devices fabricated from Cu/Cu2O/Cu patterns are produced using direct laser writing. Planar patterns are fabricated and shown to have a high sensitivity to changing laser settings used to print the oxide region. Bipolar resistive switching is observed with setting and resetting occurring near +/- 0.7V, and ratios between the high and low resistance states being as high as 102 are achieved. Fabricated devices are shown to flexible and stable over long periods of time. Memristor based logic structures Including Boolean “And” and “Or” gates are fabricated in planar patterns from memristor pairs. Logic gates show signal processing in times as short as 300ns. Moderate signal degradation from the logic gates are noted at 9% and 21% in the “Or” gate and “And” gate respectively. Memristor crossbar arrays are also fabricated from Cu/Cu2O/Cu and Ag/Cu2O/Cu patterns. Their multiple resistance states are programmed and performances are compared. In summary Direct laser writing is demonstrated as a process that has promise as a method for producing flexible novel computer hardware. Further work is recommended to focus on identifying combinations of materials and laser settings that can further improve the consistency and performance of the direct laser writing fabricated memristor devices

2022 roadmap on neuromorphic computing and engineering

Modern computation based on von Neumann architecture is now a mature cutting-edge science. In the von Neumann architecture, processing and memory units are implemented as separate blocks interchanging data intensively and continuously. This data transfer is responsible for a large part of the power consumption. The next generation computer technology is expected to solve problems at the exascale with 10$^{18}$ calculations each second. Even though these future computers will be incredibly powerful, if they are based on von Neumann type architectures, they will consume between 20 and 30 megawatts of power and will not have intrinsic physically built-in capabilities to learn or deal with complex data as our brain does. These needs can be addressed by neuromorphic computing systems which are inspired by the biological concepts of the human brain. This new generation of computers has the potential to be used for the storage and processing of large amounts of digital information with much lower power consumption than conventional processors. Among their potential future applications, an important niche is moving the control from data centers to edge devices. The aim of this roadmap is to present a snapshot of the present state of neuromorphic technology and provide an opinion on the challenges and opportunities that the future holds in the major areas of neuromorphic technology, namely materials, devices, neuromorphic circuits, neuromorphic algorithms, applications, and ethics. The roadmap is a collection of perspectives where leading researchers in the neuromorphic community provide their own view about the current state and the future challenges for each research area. We hope that this roadmap will be a useful resource by providing a concise yet comprehensive introduction to readers outside this field, for those who are just entering the field, as well as providing future perspectives for those who are well established in the neuromorphic computing community

Fundamentals

Volume 1 establishes the foundations of this new field. It goes through all the steps from data collection, their summary and clustering, to different aspects of resource-aware learning, i.e., hardware, memory, energy, and communication awareness. Machine learning methods are inspected with respect to resource requirements and how to enhance scalability on diverse computing architectures ranging from embedded systems to large computing clusters

Fundamentals

Volume 1 establishes the foundations of this new field. It goes through all the steps from data collection, their summary and clustering, to different aspects of resource-aware learning, i.e., hardware, memory, energy, and communication awareness. Machine learning methods are inspected with respect to resource requirements and how to enhance scalability on diverse computing architectures ranging from embedded systems to large computing clusters

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

The design and analysis of novel integrated phase-change photonic memory and computing devices

The current massive growth in data generation and communication challenges traditional computing and storage paradigms. The integrated silicon photonic platform may alleviate the physical limitations resulting from the use of electrical interconnects and the conventional von Neuman computing architecture, due to its intrinsic energy and bandwidth advantages. This work focuses on the development of the phase-change all-photonic memory (PPCM), a device potentially enabling the transition from the electrical to the optical domain by providing the (previously unavailable) non-volatile all-photonic storage functionality. PPCM devices allow for all-optical encoding of the information on the crystal fraction of a waveguide-implemented phase-change material layer, here Ge2Sb2Te5, which in turn modulates the transmitted signal amplitude. This thesis reports novel developments of the numerical methods necessary to emulate the physics of PPCM device operation and performance characteristics, illustrating solutions enabling the realization of a simulation framework modelling the inherently three-dimensional and self-influencing optical, thermal and phase-switching behaviour of PPCM devices. This thesis also depicts an innovative, fast and cost-effective method to characterise the key optical properties of phase-change materials (upon which the performance of PPCM devices depend), exploiting the reflection pattern of a purposely built layer stack, combined with a smart fit algorithm adapting potential solutions drawn from the scientific literature. The simulation framework developed in the thesis is used to analyse reported PPCM experimental results. Numerous sources of uncertainty are underlined, whose systematic analysis reduced to the peculiar non-linear optical properties of Ge2Sb2Te5. Yet, the data fit process validates both the simulation tool and the remaining physical assumptions, as the model captures the key aspects of the PPCM at high optical intensity, and reliably and accurately predicts its behaviour at low intensity, enabling to investigate its underpinning physical mechanisms. Finally, a novel PPCM memory architecture, exploiting the interaction of a much-reduced Ge2Sb2Te5 volume with a plasmonic resonant nanoantenna, is proposed and numerically investigated. The architecture concept is described and the memory functionality is demonstrated, underlining its potential energy and speed improvement on the conventional device by up to two orders of magnitude.Engineering and Physical Sciences Research Council (EPSRC

Dependable Embedded Systems

This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems