68 research outputs found

    LEO: Learning Efficient Orderings for Multiobjective Binary Decision Diagrams

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    Approaches based on Binary decision diagrams (BDDs) have recently achieved state-of-the-art results for multiobjective integer programming problems. The variable ordering used in constructing BDDs can have a significant impact on their size and on the quality of bounds derived from relaxed or restricted BDDs for single-objective optimization problems. We first showcase a similar impact of variable ordering on the Pareto frontier (PF) enumeration time for the multiobjective knapsack problem, suggesting the need for deriving variable ordering methods that improve the scalability of the multiobjective BDD approach. To that end, we derive a novel parameter configuration space based on variable scoring functions which are linear in a small set of interpretable and easy-to-compute variable features. We show how the configuration space can be efficiently explored using black-box optimization, circumventing the curse of dimensionality (in the number of variables and objectives), and finding good orderings that reduce the PF enumeration time. However, black-box optimization approaches incur a computational overhead that outweighs the reduction in time due to good variable ordering. To alleviate this issue, we propose LEO, a supervised learning approach for finding efficient variable orderings that reduce the enumeration time. Experiments on benchmark sets from the knapsack problem with 3-7 objectives and up to 80 variables show that LEO is ~30-300% and ~10-200% faster at PF enumeration than common ordering strategies and algorithm configuration. Our code and instances are available at https://github.com/khalil-research/leo

    On the Error Resilience of Ordered Binary Decision Diagrams

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    Ordered Binary Decision Diagrams (OBDDs) are a data structure that is used in an increasing number of fields of Computer Science (e.g., logic synthesis, program verification, data mining, bioinformatics, and data protection) for representing and manipulating discrete structures and Boolean functions. The purpose of this paper is to study the error resilience of OBDDs and to design a resilient version of this data structure, i.e., a self-repairing OBDD. In particular, we describe some strategies that make reduced ordered OBDDs resilient to errors in the indexes, that are associated to the input variables, or in the pointers (i.e., OBDD edges) of the nodes. These strategies exploit the inherent redundancy of the data structure, as well as the redundancy introduced by its efficient implementations. The solutions we propose allow the exact restoring of the original OBDD and are suitable to be applied to classical software packages for the manipulation of OBDDs currently in use. Another result of the paper is the definition of a new canonical OBDD model, called {\em Index-resilient Reduced OBDD}, which guarantees that a node with a faulty index has a reconstruction cost O(k)O(k), where kk is the number of nodes with corrupted index

    FastDOG: Fast Discrete Optimization on GPU

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    We present a massively parallel Lagrange decomposition method for solving 0--1 integer linear programs occurring in structured prediction. We propose a new iterative update scheme for solving the Lagrangean dual and a perturbation technique for decoding primal solutions. For representing subproblems we follow Lange et al. (2021) and use binary decision diagrams (BDDs). Our primal and dual algorithms require little synchronization between subproblems and optimization over BDDs needs only elementary operations without complicated control flow. This allows us to exploit the parallelism offered by GPUs for all components of our method. We present experimental results on combinatorial problems from MAP inference for Markov Random Fields, quadratic assignment and cell tracking for developmental biology. Our highly parallel GPU implementation improves upon the running times of the algorithms from Lange et al. (2021) by up to an order of magnitude. In particular, we come close to or outperform some state-of-the-art specialized heuristics while being problem agnostic. Our implementation is available at https://github.com/LPMP/BDD.Comment: Published at CVPR 2022. Alert before printing: last 10 pages just contains detailed results tabl

    Selected Topics in Network Optimization: Aligning Binary Decision Diagrams for a Facility Location Problem and a Search Method for Dynamic Shortest Path Interdiction

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    This work deals with three different combinatorial optimization problems: minimizing the total size of a pair of binary decision diagrams (BDDs) under a certain structural property, a variant of the facility location problem, and a dynamic version of the Shortest-Path Interdiction (DSPI) problem. However, these problems all have the following core idea in common: They all stem from representing an optimization problem as a decision diagram. We begin from cases in which such a diagram representation of reasonable size might exist, but finding a small diagram is difficult to achieve. The first problem develops a heuristic for enforcing a structural property for a collection of BDDs, which allows them to be merged into a single one efficiently. In the second problem, we consider a specific combinatorial problem that allows for a natural representation by a pair of BDDs. We use the previous result and ideas developed earlier in the literature to reformulate this problem as a linear program over a single BDD. This approach enables us to obtain sensitivity information, while often enjoying runtimes comparable to a mixed integer program solved with a commercial solver, after we pay the computational overhead of building the diagram (e.g., when re-solving the problem using different costs, but the same graph topology). In the last part, we examine DSPI, for which building the full decision diagram is generally impractical. We formalize the concept of a game tree for the DSPI and design a heuristic based on the idea of building only selected parts of this exponentially-sized decision diagram (which is not binary any more). We use a Monte Carlo Tree Search framework to establish policies that are near optimal. To mitigate the size of the game tree, we leverage previously derived bounds for the DSPI and employ an alphaโ€“beta pruning technique for minimax optimization. We highlight the practicality of these ideas in a series of numerical experiments

    Precise quantitative analysis of binarized neural networks: a BDD-based approach

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    As a new programming paradigm, neural-network-based machine learning has expanded its application to many real-world problems. Due to the black-box nature of neural networks, verifying and explaining their behavior are becoming increasingly important, especially when they are deployed in safety-critical applications. Existing verification work mostly focuses on qualitative verification, which asks whether there exists an input (in a specified region) for a neural network such that a property (e.g., local robustness) is violated. However, in many practical applications, such an (adversarial) input almost surely exists, which makes a qualitative answer less meaningful. In this work, we study a more interesting yet more challenging problem, i.e., quantitative verification of neural networks, which asks how often a property is satisfied or violated. We target binarized neural networks (BNNs), the 1-bit quantization of general neural networks. BNNs have attracted increasing attention in deep learning recently, as they can drastically reduce memory storage and execution time with bit-wise operations, which is crucial in recourse-constrained scenarios, e.g., embedded devices for Internet of Things. Toward quantitative verification of BNNs, we propose a novel algorithmic approach for encoding BNNs as Binary Decision Diagrams (BDDs), a widely studied model in formal verification and knowledge representation. By exploiting the internal structure of the BNNs, our encoding translates the input-output relation of blocks in BNNs to cardinality constraints, which are then encoded by BDDs. Based on the new BDD encoding, we develop a quantitative verification framework for BNNs where precise and comprehensive analysis of BNNs can be performed. To improve the scalability of BDD encoding, we also investigate parallelization strategies at various levels. We demonstrate applications of our framework by providing quantitative robustness verification and interpretability for BNNs. An extensive experimental evaluation confirms the effectiveness and efficiency of our approach

    Obfuscator Synthesis for Privacy and Utility

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    We consider the problem of synthesizing an obfuscation policy that enforces privacy while preserving utility with formal guarantees. Specifically, we consider plants modeled as finite automata with predefined secret behaviors. A given plant generates event strings for some useful computation, but meanwhile wants to hide its secret behaviors from any outside observer. We formally capture the privacy and utility specifications using the automaton model of the plant. To enforce both specifications, we propose an obfuscation mechanism where an edit function โ€œeditsโ€ the plantโ€™s output in a reactive manner. We develop algorithmic procedures that synthesize a correct-by-construction edit function satisfying both privacy and utility specifications. To address the state explosion problem, we encode the synthesis algorithm symbolically using Binary Decision Diagrams. We present EdiSyn, an implementation of our algorithms, along with experimental results demonstrating its performance on illustrative examples. This is the first work, to our knowledge, to successfully synthesize controllers satisfying both privacy and utility requirements

    Tools and Algorithms for the Construction and Analysis of Systems

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    This open access book constitutes the proceedings of the 28th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2022, which was held during April 2-7, 2022, in Munich, Germany, as part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2022. The 46 full papers and 4 short papers presented in this volume were carefully reviewed and selected from 159 submissions. The proceedings also contain 16 tool papers of the affiliated competition SV-Comp and 1 paper consisting of the competition report. TACAS is a forum for researchers, developers, and users interested in rigorously based tools and algorithms for the construction and analysis of systems. The conference aims to bridge the gaps between different communities with this common interest and to support them in their quest to improve the utility, reliability, exibility, and efficiency of tools and algorithms for building computer-controlled systems

    Tools and Algorithms for the Construction and Analysis of Systems

    Get PDF
    This open access book constitutes the proceedings of the 28th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2022, which was held during April 2-7, 2022, in Munich, Germany, as part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2022. The 46 full papers and 4 short papers presented in this volume were carefully reviewed and selected from 159 submissions. The proceedings also contain 16 tool papers of the affiliated competition SV-Comp and 1 paper consisting of the competition report. TACAS is a forum for researchers, developers, and users interested in rigorously based tools and algorithms for the construction and analysis of systems. The conference aims to bridge the gaps between different communities with this common interest and to support them in their quest to improve the utility, reliability, exibility, and efficiency of tools and algorithms for building computer-controlled systems

    ์ •ํ™•ํ•˜๊ณ  ํ•™์Šต ๊ธฐ๋ฐ˜ ์ „๋ ฅ ๋ถ„์„์„ ๊ธฐ๋ฐ˜์œผ๋กœ ํ•˜๋Š” ํด๋ก ๊ฒŒ์ดํŒ…์˜ ํ•ฉ์„ฑ

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    ํ•™์œ„๋…ผ๋ฌธ(์„์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2023. 2. ๊น€ํƒœํ™˜.In this paper, we introduce two techniques to efficiently apply clock gating in the synthesis stage. First, We propose a new clock gating methodology based on a precise power saving analysis to overcome the ineffectiveness of the conventional logic structure based clock gating. Two new features exploited in our proposed clock gating are (i) the multiplexer selection signal probability that a flip-flop with multiplexer feedback loop receives a new input and (ii) the joint probability of selection signals that two flip-flops with different multiplexor selection signals both receive new inputs at the same clock cycle. In summary, our method reduces the total power consumption by 2.46% on average (up to 5.00%) over the conventional clock gating method. In the second work, we address a new problem of transforming the long toggling/untoggling sequences of flip-flops cycle-accurate activities into short embedding vectors, so that the flip-flop grouping for clock gating is practically feasible in terms of the memory usage and run time for checking activity similarity among flip-flops. To this end, we propose a machine learning based generation of embedding vectors which are accurate enough to predict the original flip-flop toggling sequences. Precisely, we develop a neural network model of LSTM (long short-term memory) based AE(autoencoder) model combined with SDAE (stacked denoising autoencoder) to take into account the time-series (i.e., clock cycle) similarity feature among the toggling sequences, which is essential to determine which flip-flops should be grouped together for clock gating. By integrating (1) our LSTM based embedding vector generation model, we propose two additional ML models for clock gating: (2) joint state probability predictor (JSP) model for generating 0-state probability of two embedding vectors, and (3) joint feature predictor (JFP) model for generating a new embedding vector that combines two embedding vectors. Through experiments, it is confirmed that our proposed LSTM combined with AutoEnc improves the toggling sequence prediction accuracy up to 0.88 while an LSTM (long short-term memory) based AE model produces accuracy to 0.72, thereby enabling our ML based clock gating framework to save the dynamic power consumption further over that by the state-of-the-art commercial clock gating tool, which relies on the flip-flops toggling probability for grouping flip-flops. Through experiments with benchmark circuits in IWLS, it is shown that our method is able to reduce the dynamic power by 14.0% on average over that by the conventional toggling-driven clock gating.๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ํ•ฉ์„ฑ ๋‹จ๊ณ„์—์„œ ํด๋ก ๊ฒŒ์ดํŒ…์„ ํšจ์œจ์ ์œผ๋กœ ์ ์šฉํ•˜๊ธฐ ์œ„ํ•œ ๋‘ ๊ฐ€์ง€ ๊ธฐ๋ฒ•์„ ์†Œ๊ฐœํ•œ๋‹ค. ์ฒซ์งธ๋กœ, ํด๋ก ๊ฒŒ์ดํŒ… ๊ธฐ๋ฐ˜์˜ ๊ธฐ์กด ๋กœ์ง ๊ตฌ์กฐ์˜ ๋น„ํšจ์œจ์„ฑ์„ ๊ทน๋ณตํ•˜๊ธฐ ์œ„ํ•ด ์ •๋ฐ€ ํ•œ ์ ˆ์ „ ๋ถ„์„์„ ๊ธฐ๋ฐ˜์œผ๋กœ ํ•œ ์ƒˆ๋กœ์šด ํด๋ก ๊ฒŒ์ดํŒ… ๋ฐฉ๋ฒ•๋ก ์„ ์ œ์•ˆํ•œ๋‹ค. ์ œ์•ˆ๋œ ํด๋ก ๊ฒŒ์ดํŒ… ๋ฐฉ๋ฒ•์—์„œ ํ™œ์šฉ๋˜๋Š” ๋‘ ๊ฐ€์ง€ ์ƒˆ๋กœ์šด ๊ธฐ๋Šฅ์€ (i) ํ”ผ๋“œ๋ฐฑ ๋ฃจํ”„๊ฐ€ ์žˆ๋Š” ํ”Œ๋ฆฝํ”Œ๋กญ ์˜ ๋ฉ€ํ‹ฐํ”Œ๋ ‰์„œ ์„ ํƒ ์‹ ํ˜ธ ํ™•๋ฅ  ๋ฐ (ii) ์„œ๋กœ ๋‹ค๋ฅธ ๋ฉ€ํ‹ฐํ”Œ๋ ‰์„œ ์„ ํƒ ์‹ ํ˜ธ๋ฅผ ๊ฐ–๋Š” ๋‘ ํ”Œ๋ฆฝํ”Œ๋กญ์˜ ๋ฉ€ํ‹ฐํ”Œ๋ ‰์„œ ์„ ํƒ ์‹ ํ˜ธ ๊ฒฐํ•ฉ ํ™•๋ฅ ์ด๋‹ค. ์ „๋ ฅ ์ด๋“์ด ์žˆ๋Š” ๊ฒฝ์šฐ์—๋งŒ ํด๋ก ๊ฒŒ์ดํŒ…์„ ์ ์šฉํ•˜๊ณ  ์„œ๋กœ ๋‹ค๋ฅธ ํด๋ก ๊ฒŒ์ดํŒ… ๊ทธ๋ฃน์„ ํ†ตํ•ฉํ•จ์œผ๋กœ์„œ ์ „์ฒด ๋™์  ์ „๋ ฅ๋ฅผ ์ค„์ด๊ณ ์ž ํ•˜์˜€๋‹ค. ์‹คํ—˜์„ ํ†ตํ•ด ๊ธฐ์กด์˜ ํด๋ก ๊ฒŒ์ดํŒ… ๋ฐฉ๋ฒ•์— ๋น„ํ•ด ํ‰๊ท  2.46%(์ตœ๋Œ€ 5.00%)์˜ ์ด ์ „๋ ฅ ์†Œ๋น„๋ฅผ ์ค„์ด๋Š” ๊ฒƒ์„ ํ™•์ธํ•˜์˜€๋‹ค. ๋‘ ๋ฒˆ์งธ๋กœ ํ”Œ๋ฆฝํ”Œ๋กญ์˜ ํด๋ก ์ฃผ๊ธฐ๋ณ„ ์ƒํƒœ๋ฅผ ๋‚˜ํƒ€๋‚ด๋Š” ๊ธด ํ† ๊ธ€๋ง/์–ธํ† ๊ธ€๋ง ์‹œํ€€์Šค ๋ฅผ ์งง์€ ์ž„๋ฒ ๋”ฉ ๋ฒกํ„ฐ๋กœ ๋ณ€ํ™˜ํ•˜๋Š” ๋ฌธ์ œ๋ฅผ ํ•ด๊ฒฐํ•˜์˜€๋‹ค. ์ด๋ฅผ ํ† ๊ธ€๋ง ๊ธฐ๋ฐ˜ ํด๋ก ๊ฒŒ์ด ํŒ…์„ ์œ„ํ•œ ํ”Œ๋ฆฝํ”Œ๋กญ ๊ทธ๋ฃนํ™”์— ์ ์šฉํ•˜์—ฌ ํ”Œ๋ฆฝํ”Œ๋กญ ๊ฐ„์˜ ์ƒํƒœ ์œ ์‚ฌ์„ฑ ํ™•์ธ์ด ๋ฉ”๋ชจ๋ฆฌ ์‚ฌ์šฉ๋Ÿ‰ ๋ฐ ์‹คํ–‰ ์‹œ๊ฐ„ ์ธก๋ฉด์—์„œ ์‹ค์งˆ์ ์œผ๋กœ ์‹คํ˜„ ๊ฐ€๋Šฅํ•˜๊ฒŒ ํ•˜์˜€๋‹ค. ์ด๋ฅผ ์œ„ํ•ด ๊ธฐ๊ณ„ ํ•™์Šต ๊ธฐ๋ฐ˜์œผ๋กœ ์›๋ž˜์˜ ํ”Œ๋ฆฝํ”Œ๋กญ ํ† ๊ธ€ ์‹œํ€€์Šค๋ฅผ ์˜ˆ์ธกํ•˜๊ธฐ์— ์ถฉ๋ถ„ํžˆ ์ •ํ™•ํ•œ ์ €์ฐจ์›์˜ ์ž„๋ฒ ๋”ฉ ๋ฒกํ„ฐ์˜ ์ƒ์„ฑ์„ ์ œ์•ˆํ•œ๋‹ค. ์šฐ๋ฆฌ๋Š” ํ† ๊ธ€๋ง ์‹œํ€€์Šค ๊ฐ„์˜ ์‹œ๊ณ„์—ด ์œ ์‚ฌ์„ฑ์„ ๊ณ ๋ ค ํ•˜๊ธฐ ์œ„ํ•ด ๋””๋…ธ์ด์ฆˆ ์˜คํ† ์ธ์ฝ”๋”๋ฅผ ์ด์šฉํ•˜์—ฌ 5000 ํด๋ก ์‚ฌ์ดํด์˜ ํ† ๊ธ€๋ง ์‹œํ€€์Šค๋ฅผ 10์ฐจ์›์œผ๋กœ ์••์ถ•ํ•˜๊ณ  ์ด๋ฅผ ์žฅ๋‹จ๊ธฐ ๋ฉ”๋ชจ๋ฆฌ ์˜คํ† ์ธ์ฝ”๋”์— ์ž…๋ ฅํ•˜์—ฌ ์ „์ฒด ์‹œํ€€์Šค๋ฅผ ๋Œ€๋ณ€ํ•˜๋Š” ์ €์ฐจ์› ์ž„๋ฒ ๋”ฉ ๋ฒกํ„ฐ๋ฅผ ์ƒ์„ฑํ•˜๋Š” ์‹ ๊ฒฝ๋ง ๋ชจ๋ธ์„ ๊ฐœ๋ฐœํ•˜์˜€๋‹ค. ๋˜ํ•œ ์šฐ๋ฆฌ๋Š” ํด๋ก ๊ฒŒ์ดํŒ…์„ ์œ„ํ•œ ๋‘ ๊ฐ€์ง€ ๋ถ€๊ฐ€์ ์ธ ์‹ ๊ฒฝ๋ง ๋ชจ๋ธ์ธ (1) 2๊ฐœ์˜ ์ž„๋ฒ ๋”ฉ ๋ฒกํ„ฐ์˜ 0- ์ƒํƒœ ํ™•๋ฅ  ์ƒ์„ฑ์„ ์œ„ํ•œ ๊ฒฐํ•ฉ ํ™•๋ฅ  ์˜ˆ์ธก ๋ชจ๋ธ๊ณผ (2) ๋‘ ๊ฐœ์˜ ์ž„๋ฒ ๋”ฉ ๋ฒกํ„ฐ๋ฅผ ๊ฒฐํ•ฉํ•˜์—ฌ ์ƒˆ๋กœ์šด ์ž„๋ฒ ๋”ฉ ๋ฒกํ„ฐ๋ฅผ ์˜ˆ์ธกํ•˜๋Š” ๊ฒฐํ•ฉ ํŠน์ง• ์˜ˆ์ธก ๋ชจ๋ธ์„ ์ œ์•ˆํ•œ๋‹ค. IWLS ๋ฒค์น˜๋งˆํฌ ํšŒ๋กœ๋ฅผ ์ด์šฉํ•œ ์‹คํ—˜์„ ํ†ตํ•ด, ๋””๋…ธ์ด์ฆˆ ์˜คํ† ์ธ์ฝ”๋”๋งŒ ์‚ฌ์šฉํ–ˆ์„๋•Œ๋ณด๋‹ค ์žฅ๋‹จ๊ธฐ ๋ฉ”๋ชจ๋ฆฌ ๊ธฐ๋ฐ˜์˜ ์˜คํ† ์ธ์ฝ”๋”๋ฅผ ๊ฒฐํ•ฉํ–ˆ์„ ๋•Œ ์ž…๋ ฅ ๋ฐ์ดํ„ฐ๋ฅผ ๋ณต์› ์ •ํ™•๋„๊ฐ€ ๋” ์šฐ์ˆ˜ํ•œ ๊ฒƒ์„ ํ™• ์ธํ•˜์˜€๋‹ค. ๋˜ํ•œ ์šฐ๋ฆฌ์˜ ๋ฐฉ๋ฒ•์ด ๊ธฐ์กด์˜ ํ† ๊ธ€๋ง ๊ธฐ๋ฐ˜ ํด๋ก ๊ฒŒ์ดํŒ…์— ๋น„ํ•ด ํ‰๊ท  14.0% ์˜ ๋™์  ์ „๋ ฅ์„ ์ค„์ผ ์ˆ˜ ์žˆ์Œ์„ ํ™•์ธํ•˜์˜€๋‹ค.1 Selective Clock Gating Based on Comprehensive Power Saving Analysis 1 1.1 Introduction 1 1.2 Preliminary and Motivation 1 1.3 Selective Clock Gating 3 1.3.1 Concept of Selective Clock Gating 3 1.3.2 Joint probability of selection signals 5 1.4 Experimental Results 6 1.4.1 Experimental Setup 6 1.4.2 Experimental Result 7 1.5 Conclusion 10 2 Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating 11 2.1 Introduction 11 2.2 Preliminaries and Prior Works 13 2.2.1 Preliminary and Motivation 13 2.2.2 Prior Works 14 2.3 Machine Learning Based Clock Gating Framework 14 2.3.1 Primary Model: Embedding Vector Generation 14 2.3.2 Secondary Models: Joint State Probability and Joint Feature Prediction 17 2.3.3 Distance Analysis Between Embedding Vectors 18 2.3.4 Power Analysis Model 19 2.3.5 Overall Flow of Flip-flop Grouping 19 2.4 Experimental Results 19 2.4.1 Comparison of Dynamic Power Saving 20 2.4.2 Performance of Auto-encoder Reconstruction Model 21 2.5 Conclusion 21 Abstract (In Korean) 26์„
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