Mitigation of impulsive noise for SISO and MIMO G.fast system

To address the demand for high bandwidth data transmission over telephone transmission lines, International Telecommunication Union (ITU) has recently completed the fourth generation broadband (4GBB) copper access network technology, known as G.fast. Throughout this thesis, extensively investigates the wired broadband G.fast coding system and the novel impulsive noise reduction technique has been proposed to improve the performance of wired communications network in three different scenarios: single-line Discrete Multiple Tone (DMT)- G.fast system; a multiple input multiple-output (MIMO) DMTG.fast system, and MIMO G.fast system with different crosstalk cancellation methods. For each of these scenarios, however, Impulsive Noise (IN) is considered as the main limiting factor of performance system. In order to improve the performance of such systems, which use higher order QAM constellation such as G.fast system, this thesis examines the performance of DMT G.fast system over copper channel for six different higher signal constellations of M = 32, 128, 512, 2048, 8192 and 32768 in presence of IN modelled as the Middleton Class A (MCA) noise source. In contrast to existing work, this thesis presents and derives a novel equation of Optimal Threshold (OT) to improve the IN frequency domain mitigation methods applied to the G.fast standard over copper channel with higher QAM signal constellations. The second scenario, Multi-Line Copper Wire (MLCW) G.fast is adopted utilizing the proposed MLCW Chen model and is compared to a single line G-fast system by a comparative analysis in terms of Bit-Error-Rate(BER) performance of implementation of MLCW-DMT G.fast system. The third scenario, linear and non-linear crosstalk crosstalk interference cancellation methods are applied to MLCW G.fas and compared by a comparative analysis in terms of BER performance and the complexity of implementation.University of Technology for choosing me for their PhD scholarship and The Higher Committee For Education Development in Iraq(HCED

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process