An optofluidic router in a low-cost (PDMS) platform for rapid parallel sample analysis

En col·laboració amb la Universitat de Barcelona (UB), la Universitat Autònoma de Barcelona (UAB) i l'Institut de Ciències Fotòniques (ICFO)Optofluidic system for (bio)chemical applications are becoming more demanding in terms of num- ber of control points, number of light sources and readout equipment. So far, most of these sys- tems require several light sources/detectors for suitable performance, increasing their complexity and cost. In this work, we present an easily integrated, fluidically controlled optical router that fa- cilitates coupling of several light sources or detectors. By using PDMS mirrors and phaseguides, the switching liquid is guided and pinned in desired angles, so that the incident light undergoes total internal reflection and can be reflected towards the output channels without any movable parts. The developed router presents ideal performance for lab on a chip applications, achieving switching frequencies between 0.07 ± 0.025 and 4 ± 2 Hz, depending on the flow rate of the switching liquid. The cross-talk levels are at 20 dB from channel output power to static noise level. With the use of parabolic mirrors, channel coupling efficiencies decrease just 2.38 dBm over four channels. The dynamic switching noise reduces the cross-talk levels by 2-5 dB, depending on the incorporation of ink-apertures. The insertion loss of these devices ranges from 17.34 to 25.42 dB. These results prove the viability of the fluidically controlled router in the low-cost PDMS platform. The intended goal of this work has been to simplify and speed up parallel sample analysis with the router integrated into a multiple path photonic component on a single chip. Development on this front is ongoing to rapidly measure methadone concentrations on chip

Extending the performance of hybrid NoCs beyond the limitations of network heterogeneity

To meet the performance and scalability demands of the fast-paced technological growth towards exascale and Big-Data processing with the performance bottleneck of conventional metal based interconnects (wireline), alternative interconnect fabrics such as inhomogeneous three-dimensional integrated Network-on-Chip (3D NoC) and hybrid wired-wireless Network-on-Chip (WiNoC) have emanated as a cost-effective solution for emerging System-on-Chip (SoC) design. However, these interconnects trade-off optimized performance for cost by restricting the number of area and power hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in chip multiprocessor (CMP) demands an on-chip communication infrastructure which can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. The proposed router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads. When the output port required for intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able balance the traffic in hybrid NoCs to achieve low-latency communication under various traffic loads. Simulation shows that, the proposed router can reduce applications’ execution time by an average of 16.9% compared to low-latency routers such as SWIFT. By reducing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes) the proposed router can improve performance efficiency in terms of average packet delay by an average of 45% (or 50%) in 3D NoCs (or WiNoCs)

A survey on scheduling and mapping techniques in 3D Network-on-chip

Network-on-Chips (NoCs) have been widely employed in the design of multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs enable communications between on-chip Intellectual Property (IP) cores and allow those cores to achieve higher performance by outsourcing their communication tasks. Mapping and Scheduling methodologies are key elements in assigning application tasks, allocating the tasks to the IPs, and organising communication among them to achieve some specified objectives. The goal of this paper is to present a detailed state-of-the-art of research in the field of mapping and scheduling of applications on 3D NoC, classifying the works based on several dimensions and giving some potential research directions