5,463 research outputs found

    An improved double-toroidal spectrometer for gas phase (e,2e) studies

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    A new spectrometer is described for measuring the momentum distributions of scattered electrons arising from electron-atom and electron-molecule ionization experiments. It incorporates and builds on elements from a number of previous designs, namely, a source of polarized electrons and two high-efficiency electrostatic electron energy analyzers. The analyzers each comprise a seven-element retarding-electrostatic lens system, four toroidal-sector electrodes, and a fast position-and-time-sensitive two-dimensional delay-line detector. Results are presented for the electron-impact-induced ionization of helium and the elastic scattering of electrons from argon and helium which demonstrate that high levels of momentum resolution and data-collection efficiency are achieved. Problematic aspects regarding variations in collection efficiency over the accepted momentum phase space are addressed and a methodology for their correction presented. Principles behind the present design and previous designs for electrostatic analyzers based around electrodes of toroidal-sector geometry are discussed and a framework is provided for optimizing future devices.The assistance of the AustralianGerman Research Cooperation Scheme and the Australian Research Council through Grant No. DP0452553 and a 1998 ARC RIEF grant is gratefully acknowledged

    Wide-band mixing DACs with high spectral purity

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    Model-Guided Data-Driven Optimization and Control for Internal Combustion Engine Systems

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    The incorporation of electronic components into modern Internal Combustion, IC, engine systems have facilitated the reduction of fuel consumption and emission from IC engine operations. As more mechanical functions are being replaced by electric or electronic devices, the IC engine systems are becoming more complex in structure. Sophisticated control strategies are called in to help the engine systems meet the drivability demands and to comply with the emission regulations. Different model-based or data-driven algorithms have been applied to the optimization and control of IC engine systems. For the conventional model-based algorithms, the accuracy of the applied system models has a crucial impact on the quality of the feedback system performance. With computable analytic solutions and a good estimation of the real physical processes, the model-based control embedded systems are able to achieve good transient performances. However, the analytic solutions of some nonlinear models are difficult to obtain. Even if the solutions are available, because of the presence of unavoidable modeling uncertainties, the model-based controllers are designed conservatively

    Accelerated Aging in Devices and Circuits

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    abstract: The aging mechanism in devices is prone to uncertainties due to dynamic stress conditions. In AMS circuits these can lead to momentary fluctuations in circuit voltage that may be missed by a compact model and hence cause unpredictable failure. Firstly, multiple aging effects in the devices may have underlying correlations. The generation of new traps during TDDB may significantly accelerate BTI, since these traps are close to the dielectric-Si interface in scaled technology. Secondly, the prevalent reliability analysis lacks a direct validation of the lifetime of devices and circuits. The aging mechanism of BTI causes gradual degradation of the device leading to threshold voltage shift and increasing the failure rate. In the 28nm HKMG technology, contribution of BTI to NMOS degradation has become significant at high temperature as compared to Channel Hot Carrier (CHC). This requires revising the End of Lifetime (EOL) calculation based on contribution from induvial aging effects especially in feedback loops. Conventionally, aging in devices is extrapolated from a short-term measurement, but this practice results in unreliable prediction of EOL caused by variability in initial parameters and stress conditions. To mitigate the extrapolation issues and improve predictability, this work aims at providing a new approach to test the device to EOL in a fast and controllable manner. The contributions of this thesis include: (1) based on stochastic trapping/de-trapping mechanism, new compact BTI models are developed and verified with 14nm FinFET and 28nm HKMG data. Moreover, these models are implemented into circuit simulation, illustrating a significant increase in failure rate due to accelerated BTI, (2) developing a model to predict accelerated aging under special conditions like feedback loops and stacked inverters, (3) introducing a feedback loop based test methodology called Adaptive Accelerated Aging (AAA) that can generate accurate aging data till EOL, (4) presenting simulation and experimental data for the models and providing test setup for multiple stress conditions, including those for achieving EOL in 1 hour device as well as ring oscillator (RO) circuit for validation of the proposed methodology, and (5) scaling these models for finding a guard band for VLSI design circuits that can provide realistic aging impact.Dissertation/ThesisMasters Thesis Electrical Engineering 201

    Progress of analog-hybrid computation

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    Review of fast analog/hybrid computer systems, integrated operational amplifiers, electronic mode-control switches, digital attenuators, and packaging technique

    Design, Commissioning and Performance of the PIBETA Detector at PSI

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    We describe the design, construction and performance of the PIBETA detector built for the precise measurement of the branching ratio of pion beta decay, pi+ -> pi0 e+ nu, at the Paul Scherrer Institute. The central part of the detector is a 240-module spherical pure CsI calorimeter covering 3*pi sr solid angle. The calorimeter is supplemented with an active collimator/beam degrader system, an active segmented plastic target, a pair of low-mass cylindrical wire chambers and a 20-element cylindrical plastic scintillator hodoscope. The whole detector system is housed inside a temperature-controlled lead brick enclosure which in turn is lined with cosmic muon plastic veto counters. Commissioning and calibration data were taken during two three-month beam periods in 1999/2000 with pi+ stopping rates between 1.3*E3 pi+/s and 1.3*E6 pi+/s. We examine the timing, energy and angular detector resolution for photons, positrons and protons in the energy range of 5-150 MeV, as well as the response of the detector to cosmic muons. We illustrate the detector signatures for the assorted rare pion and muon decays and their associated backgrounds.Comment: 117 pages, 48 Postscript figures, 5 tables, Elsevier LaTeX, submitted to Nucl. Instrum. Meth.

    로직 및 피지컬 합성에서의 타이밍 분석과 최적화

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    학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 김태환.Timing analysis is one of the necessary steps in the development of a semiconductor circuit. In addition, it is increasingly important in the advanced process technologies due to various factors, including the increase of process–voltage–temperature variation. This dissertation addresses three problems related to timing analysis and optimization in logic and physical synthesis. Firstly, most static timing analysis today are based on conventional fixed flip-flop timing models, in which every flip-flop is assumed to have a fixed clock-to-Q delay. However, setup and hold skews affect the clock-to-Q delay in reality. In this dissertation, I propose a mathematical formulation to solve the problem and apply it to the clock skew scheduling problems as well as to the analysis of a given circuit, with a scalable speedup technique. Secondly, near-threshold computing is one of the promising concepts for energy-efficient operation of VLSI systems, but wide performance variation and nonlinearity to process variations block the proliferation. To cope with this, I propose a holistic hardware performance monitoring methodology for accurate timing prediction in a near-threshold voltage regime and advanced process technology. Lastly, an asynchronous circuit is one of the alternatives to the conventional synchronous style, and asynchronous pipeline circuit especially attractive because of its small design effort. This dissertation addresses the synthesis problem of lightening two-phase bundled-data asynchronous pipeline controllers, in which delay buffers are essential for guaranteeing the correct handshaking operation but incurs considerable area increase.타이밍 분석은 반도체 회로 개발 필수 과정 중 하나로, 최신 공정일수록 공정-전압-온도 변이 증가를 포함한 다양한 요인으로 하여금 그 중요성이 커지고 있다. 본 논문에서는 로직 및 피지컬 합성과 관련하여 세 가지 타이밍 분석 및 최적화 문제에 대해 다룬다. 첫째로, 오늘날 대부분의 정적 타이밍 분석은 모든 플립-플롭의 클럭-출력 딜레이가 고정된 값이라는 가정을 바탕으로 이루어졌다. 하지만 실제 클럭-출력 딜레이는 해당 플립-플롭의 셋업 및 홀드 스큐에 영향을 받는다. 본 논문에서는 이러한 특성을 수학적으로 정리하였으며, 이를 확장 가능한 속도 향상 기법과 더불어 주어진 회로의 타이밍 분석 및 클럭 스큐 스케쥴링 문제에 적용하였다. 둘째로, 유사 문턱 연산은 초고집적 회로 동작의 에너지 효율을 끌어 올릴 수 있다는 점에서 각광받지만, 큰 폭의 성능 변이 및 비선형성 때문에 널리 활용되고 있지 않다. 이를 해결하기 위해 유사 문턱 전압 영역 및 최신 공정 노드에서 보다 정확한 타이밍 예측을 위한 하드웨어 성능 모니터링 방법론 전반을 제안하였다. 마지막으로, 비동기 회로는 기존 동기 회로의 대안 중 하나로, 그 중에서도 비동기 파이프라인 회로는 비교적 적은 설계 노력만으로도 구현 가능하다는 장점이 있다. 본 논문에서는 2위상 묶음 데이터 프로토콜 기반 비동기 파이프라인 컨트롤러 상에서, 정확한 핸드셰이킹 통신을 위해 삽입된 딜레이 버퍼에 의한 면적 증가를 완화할 수 있는 합성 기법을 제시하였다.1 INTRODUCTION 1 1.1 Flexible Flip-Flop Timing Model 1 1.2 Hardware Performance Monitoring Methodology 4 1.3 Asynchronous Pipeline Controller 10 1.4 Contributions of this Dissertation 15 2 ANALYSIS AND OPTIMIZATION CONSIDERING FLEXIBLE FLIP-FLOP TIMING MODEL 17 2.1 Preliminaries 17 2.1.1 Terminologies 17 2.1.2 Timing Analysis 20 2.1.3 Clock-to-Q Delay Surface Modeling 21 2.2 Clock-to-Q Delay Interval Analysis 22 2.2.1 Derivation 23 2.2.2 Additional Constraints 26 2.2.3 Analysis: Finding Minimum Clock Period 28 2.2.4 Optimization: Clock Skew Scheduling 30 2.2.5 Scalable Speedup Technique 33 2.3 Experimental Results 37 2.3.1 Application to Minimum Clock Period Finding 37 2.3.2 Application to Clock Skew Scheduling 39 2.3.3 Efficacy of Scalable Speedup Technique 43 2.4 Summary 44 3 HARDWARE PERFORMANCE MONITORING METHODOLOGY AT NTC AND ADVANCED TECHNOLOGY NODE 45 3.1 Overall Flow of Proposed HPM Methodology 45 3.2 Prerequisites to HPM Methodology 47 3.2.1 BEOL Process Variation Modeling 47 3.2.2 Surrogate Model Preparation 49 3.3 HPM Methodology: Design Phase 52 3.3.1 HPM2PV Model Construction 52 3.3.2 Optimization of Monitoring Circuits Configuration 54 3.3.3 PV2CPT Model Construction 58 3.4 HPM Methodology: Post-Silicon Phase 60 3.4.1 Transfer Learning in Silicon Characterization Step 60 3.4.2 Procedures in Volume Production Phase 61 3.5 Experimental Results 62 3.5.1 Experimental Setup 62 3.5.2 Exploration of Monitoring Circuits Configuration 64 3.5.3 Effectiveness of Monitoring Circuits Optimization 66 3.5.4 Considering BEOL PVs and Uncertainty Learning 68 3.5.5 Comparison among Different Prediction Flows 69 3.5.6 Effectiveness of Prediction Model Calibration 71 3.6 Summary 73 4 LIGHTENING ASYNCHRONOUS PIPELINE CONTROLLER 75 4.1 Preliminaries and State-of-the-Art Work 75 4.1.1 Bundled-data vs. Dual-rail Asynchronous Circuits 75 4.1.2 Two-phase vs. Four-phase Bundled-data Protocol 76 4.1.3 Conventional State-of-the-Art Pipeline Controller Template 77 4.2 Delay Path Sharing for Lightening Pipeline Controller Template 78 4.2.1 Synthesizing Sharable Delay Paths 78 4.2.2 Validating Logical Correctness for Sharable Delay Paths 80 4.2.3 Reformulating Timing Constraints of Controller Template 81 4.2.4 Minimally Allocating Delay Buffers 87 4.3 In-depth Pipeline Controller Template Synthesis with Delay Path Reusing 88 4.3.1 Synthesizing Delay Path Units 88 4.3.2 Validating Logical Correctness of Delay Path Units 89 4.3.3 Updating Timing Constraints for Delay Path Units 91 4.3.4 In-depth Synthesis Flow Utilizing Delay Path Units 95 4.4 Experimental Results 99 4.4.1 Environment Setup 99 4.4.2 Piecewise Linear Modeling of Delay Path Unit Area 99 4.4.3 Comparison of Power, Performance, and Area 102 4.5 Summary 107 5 CONCLUSION 109 5.1 Chapter 2 109 5.2 Chapter 3 110 5.3 Chapter 4 110 Abstract (In Korean) 127Docto

    Spatial channel characterization for smart antenna solutions in FDD wireless networks

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    This paper introduces a novel metric for determining the spatial decorrelation between the up- and down-link wireless bearers in frequency division duplex (FDD) networks. This metric has direct relevance to smart or adaptive antenna array base-station deployments in cellular networks, which are known to offer capacity enhancement when compared to fixed coverage solutions. In particular, the results presented were obtained from field trial measurement campaigns for both urban and rural scenarios, with the observations having a direct impact on the choice of down-link beamforming architecture in FDD applications. Further, it is shown that significant spatial decorrelation can occur in urban deployments for bearer separations as small as 5 MHz. Results are presented in terms of both instantaneous characteristics as well as time averaged estimates, thus facilitating the appraisal of smart antenna solutions in both packet and circuit switched network
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