Channel Characterization for Chip-scale Wireless Communications within Computing Packages

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.Comment: To be presented 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018); Torino, Italy; October 201

Channel characterization for chip-scale wireless communications within computing packages

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.Peer ReviewedPostprint (author's final draft

Recent Trends and Considerations for High Speed Data in Chips and System Interconnects

This paper discusses key issues related to the design of large processing volume chip architectures and high speed system interconnects. Design methodologies and techniques are discussed, where recent trends and considerations are highlighted

Design of 28 GHz 4x4 RF Beamforming Array for 5G Radio Front-Ends

Current state of wireless infrastructure sees mass migration to higher frequencies as much of the already used spectrum is insufficient in supporting the influx of numerous users and various data intensive mobile applications. Data rates are projected to increase by an order of magnitude and harnessing the necessary bandwidth below 6 GHz is not feasible. A move to higher frequencies sees not only increased fractional bandwidth, but also significantly enhanced antenna apertures as a result of beamforming capabilities. Due to device level complications with frequencies nearing the unit gain frequency of transistor technology, high output power is seldom found, and in conjunction with severe path loss, communication links cannot be established without the usage of antenna arrays. Phased array systems offer significant upside to the traditional array implementation as it permits reconfigurable directive communication. However, Ka-Band phased arrays still struggle to arrive at a reasonable tradeoff between design complexity, cost and performance. With a divide between both organic and printed circuit board (PCB) based approaches to the development of an antenna-in-package (AiP), this thesis sides with the latter. An antenna-on-PCB variant of the AiP is developed, which implements both commercially available RF laminates and RFIC front end modules to produce a 28 GHz 4x4 RF beamforming phased array that is found to exhibit extremely low loss (-0.66 dB), adequate scan volume (+/- 45 degrees, in E and H planes) and large bandwidth (3 GHz) for a single layer, non-isolated patch antenna design. Unit cell, infinite array analysis is emphasized and lattice resizing is leveraged to obtain desired scan performance, while significantly reducing design complexity via the absence of intricate isolation enhancement techniques. In an effort to aid in application based design, the AiP is extended to application of linearization where it is found that the inclusion of dummy elements along the perimeter of the package not only serve as element pattern enhancement, but also provide reliable means of output signal capture. Negating the traditional transmitter observation receiver (TOR) architecture, the AiP design as a TOR for millimeter-wave communication proves optimistic in the quest for maximum system efficiency

Low Temperature Co-fired Ceramics for System-in-Package Applications at 122 GHz

This work presents a low temperature co-fired ceramic (LTCC) technology based system-in-package (SiP) operating beyond 100 GHz. The SiP encloses a semiconductor transceiver chip in a pea-sized LTCC package. The SiP is efficient and robust in terms of its electrical, thermal and mechanical characteristics. Moreover, it is low-cost and requires only standard manufacturing and assembly techniques. Finally, two fully-integrated 122 GHz radar sensors are demonstrated in LTCC technology