A Novel VLSI Technology to Manufacture High-Density Thermoelectric Cooling Devices

This paper describes a novel integrated circuit technology to manufacture high-density thermoelectric devices on a semiconductor wafer. With no moving parts, a thermoelectric cooler operates quietly, allows cooling below ambient temperature, and may be used for temperature control or heating if the direction of current flow is reversed. By using a monolithic process to increase the number of thermoelectric couples, the proposed solid-state cooling technology can be combined with traditional air cooling, liquid cooling, and phase-change cooling to yield greater heat flux and provide better cooling capability.Comment: Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions

Development of a Thermoelectric Characterization Platform for Electrochemically Deposited Materials

Die erfolgreiche Optimierung der Leistung von thermoelektrischen Materialien, die durch zT beschrieben wird, ist entscheidend für ihre Anwendung für das Wärmemanagement und die Kühlung von Leistungselektronik. Im Gegensatz zu Bulk-Proben bleibt die vollständige zT-Charakterisierung von Dünn- und Dickfilmmaterialien eine große Herausforderung. Dies ist insbesondere relevant für Filme, die durch elektrochemische Abscheidung synthetisiert werden, wo das Material auf eine elektrisch leitende Schicht abgeschieden wird. In dieser Dissertation habe ich ein Transport-Device für eine vollständige zTCharakterisierung von elektrochemisch abgeschiedenen Materialien entwickelt, während der Einfluss der elektrisch leitenden Schicht, sowie des Substrats beseitigt wird. Die zT-Charakterisierung erfolgt unter Verwendung eines auf einer freistehenden Membran suspendierten thermoelektrischen Materials innerhalb des entwickelten Transport-Devices, die durch eine Kombination von Fotolithografie und Mikrostrukturierungstechnik zusammen mit Ätzprozessen hergestellt wurde. Für die Messung der Wärmeleitfähigkeit habe ich eine eindimensionale, analytische, stationäre Methode eingesetzt, welche mit Hilfe von dreidimensionalen Finite-Elemente-Simulationen bestätigt wurde. Darüber hinaus habe ich die temperaturabhängigen thermoelektrischen Eigenschaften von zwei Dickschichten mit Hilfe des entwickelten Devices untersucht und mit Bulk-Proben und Dünnfilmen verglichen. Auf diese Weise konnte die Validität des Transport-Devices nachgewiesen werden. Neben der Optimierung von mikro-thermoelektrischen Materialien, die mit dem Transport- Device charakterisiert werden, ist die Leistung von thermoelektrischen Devices von den Faktoren Design, Geometrie und Konstruktion beeinflusst. Daher habe ich den Einfluss der Geometrie auf die Leistung eines elektrochemisch hergestellten mikrothermoelektrischen Generators mit Hilfe einer Finite-Elemente-Simulation untersucht

Theoretical study of thermoelectric cooling system performance

This work provides a theoretical investigation to study the effect of different operational parameters on theperformance of TE cooling system including the system COP and the rate of heat transfer. The parametersinvestigated are, the applied input power, inlet working fluid velocity, the arrangement of utilized TECs modules andfluid type. The geometry is created with ANSYS multi-physics software as a two-dimensional base case, it isconsisted from two attached horizontal ducts of length (520 mm) and (560 mm), the interface surface between the twoducts contains three thermoelectric modules (4 mm height by 40 mm wide and 40 mm length). The distance betweentwo consecutive thermoelectric modules (150 mm), the inlet and outlet duct diameter (15 mm) and the height of eachduct (10 cm), the inlet voltage to thermoelectric modules ranges from 8.0 V to 12 V and the water inlet velocity to thetwo ducts from 0.001 to 0.01 m/s. Theoretical results showed that the overall COP of TE cooling system is increasedwith the applied input power up to 8.0 W then it decreases with input power up to 18 W after that it takes nearly aconstant value, a noticeable enhancement in the COP is found when the three TECs are in use (Case 10) and the COPof TE cooling system using pure water and nanofluid with 0.05% of nanoparticles as coolants takes the maximumvalue

On-Chip Thermoelectric Hotspot Cooling

Increased power density and non-uniform heat dissipation present a thermal management challenge in modern electronic devices. The non-homogeneous heating in chips results in areas of elevated temperature, which even if small and localized, limit overall device performance and reliability. In power electronics, hotspot heat fluxes can be in excess of 1kW/cm2. Although novel package-level and chip-level cooling systems capable of removing the large amounts of dissipated heat are under development, such “global” cooling systems typically reduce the chip temperature uniformly, leaving the temperature non-uniformity unaddressed. Thus, advanced hotspot cooling techniques, which provide localized cooling to areas of elevated heat flux, are required to supplement the new “global” cooling systems and unlock the full potential of cutting-edge power devices. Thermoelectric coolers have previously been demonstrated as an effective method of producing on-demand, localized cooling for semiconductor photonic and logic devices. The growing need for the removal of localized hotspots has turned renewed attention to on-chip thermoelectric cooling, seeking to raise the maximum allowable heat flux of thermoelectrically-cooled semiconductor device hotspots. This dissertation focused on the numerical and empirical determination of the operational characteristics and performance limits of two specific thermoelectric methods for high heat flux hotspot cooling: monolithic thermoelectric hotspot cooling and micro-contact enhanced thermoelectric hotspot cooling. The monolithic cooling configuration uses the underlying electronic substrate as the thermoelectric material, eliminating the need for a discrete cooler and its associated thermal interface resistance. Micro-contact enhanced cooling uses a contact structure to concentrate the cooling produced by the thermoelectric module, enabling the direct removal of kW/cm2 level heat fluxes from on-chip hotspots. To facilitate empirical validation of on-chip thermoelectric coolers and characterization of advanced thin film thermoelectric coolers, it was found necessary to develop a novel laser heating system, using a high power laser and short-focal length optics. The design and use of this illumination system, capable of creating kW/cm2-level, mm-sized hotspots, will also be described

On-Chip Thermoelectric Cooling of Semiconductor Hot Spot

The Moore's Law progression in semiconductor technology, including shrinking feature size, increasing transistor density, and faster circuit speeds, is leading to increasing total power dissipations and heat fluxes on silicon chip. Moreover, in recent years, increasing performance has resulted in greater non-uniformity of on-chip power dissipation, creating microscale hot spots that can significantly degrade the processor performance and reliability. Application of conventional thermal packaging technology, developed to provide uniform chip cooling, to such chip designs results in lower allowable chip power dissipation or overcooling of large areas of the chip. Consequently, novel thermoelectric cooler (TEC) has been proposed recently for on-chip hot spot cooling because of its unique ability to selectively cool down the localized microscale hot spot. In this dissertation the potential application of thermoelectric coolers to suppress on-chip hotspots is explored using analytical modeling, numerical simulation, and experimental techniques. Single-crystal silicon is proposed as a potential thermoelectric material due to its high Seebeck coefficient and its thermoelectric cooling performance is investigated using device-level analytical modeling. Integrated on silicon chip as an integral, on-chip thermoelectric cooler, silicon microcooler can effectively reduce the hotspot temperature and its effectiveness is investigated using analytical modeling and numerical simulation, and found to be dependent of doping concentration in silicon, electric contact resistance, hotspot size, hotspot heat flux, die thickness and microcooler size. The other novel on-chip hotspot cooling solution developed in this dissertation is to use a mini-contact enhanced TEC, where the mini-contact pad connects the silicon chip and the TEC to concentrate the thermoelectric cooling power onto a spot of top surface of the silicon chip and therefore significantly improve the hotspot cooling performance. Numerical simulation shows hotspot cooling is determined by thermal contact resistance, thermoelectric element thickness, chip thickness, etc. Package-level experiment demonstrates that spot cooling performance of such mini-contact enhanced TEC can be improved by about 100%

Opportunities for mesoscopics in thermometry and refrigeration: Physics and applications

This review presents an overview of the thermal properties of mesoscopic structures. The discussion is based on the concept of electron energy distribution, and, in particular, on controlling and probing it. The temperature of an electron gas is determined by this distribution: refrigeration is equivalent to narrowing it, and thermometry is probing its convolution with a function characterizing the measuring device. Temperature exists, strictly speaking, only in quasiequilibrium in which the distribution follows the Fermi-Dirac form. Interesting nonequilibrium deviations can occur due to slow relaxation rates of the electrons, e.g., among themselves or with lattice phonons. Observation and applications of nonequilibrium phenomena are also discussed. The focus in this paper is at low temperatures, primarily below 4 K, where physical phenomena on mesoscopic scales and hybrid combinations of various types of materials, e.g., superconductors, normal metals, insulators, and doped semiconductors, open up a rich variety of device concepts. This review starts with an introduction to theoretical concepts and experimental results on thermal properties of mesoscopic structures. Then thermometry and refrigeration are examined with an emphasis on experiments. An immediate application of solid-state refrigeration and thermometry is in ultrasensitive radiation detection, which is discussed in depth. This review concludes with a summary of pertinent fabrication methods of presented devices.Comment: Close to the version published in RMP; 59 pages, 35 figure

HOTSPOT REMEDIATION USING GERMANIUM SELF COOLING TECHNOLOGY

Localized thermoelectric "self cooling" in semiconductor materials is among the most promising approaches for the remediation of on-chip hot spots resulting from the shrinking feature sizes and faster switching speeds of nanoelectronic components. Self cooling in a germanium chip is investigated, using 3-dimensional, thermal-electric, coupled numerical simulations, for a range of systems and geometric parameters. The results suggest that localized cooling, associated with the introduction of an electric current on the back surface of a germanium chip, can effectively reduce the hot spot temperature rise on the active side of the chip. It was found that self cooling in a 100µm thick chip could provide between 3.9ºC and 4.5ºC hotspot temperature reduction. When using a germanium layer above an electrically insulated silicon layer, self-cooling was found to yield an additional 1ºC to 2º C temperature reduction. A streamlined computational tool is developed to facilitate the identification of optimal cooling parameters

Miniature Thermoelectric Coolers for On-Chip Hot Spots

Following Moore's Law, semiconductor transistor density has doubled roughly every 18 months to alleviate increasing IC performance demands. Growing microprocessor complexity and performance, coupled with the functional integration of logic and memory components in chip architecture, have led to highly non-uniform on-chip power distribution. The resulting localized high heat flux "hot spots" are becoming a major difficulty due to their propensity for degrading microprocessor performance and for significantly reducing chip reliability. Most conventional cooling techniques provide uniform cooling to the device and do not focus much attention on the hot spots themselves. Therefore, other innovative and novel thermal management techniques must be explored to aggressively and selectively combat the deleterious effects of on-chip hot spots. This thesis explores two previously proposed thermal management techniques utilizing thermoelectrics to cool on-chip hot spots: the silicon microcooler with an integrated SiGe superlattice layer and the mini-contact enhanced conventional thermoelectric cooler (TEC)

Energy efficient active cooling of integrated circuits using embedded thermoelectric devices

With technology scaling, the amount of transistors on a single chip doubles itself every 18 months giving rise to increased power density levels. This has directly lead to a rapid increase of thermal induced issues on a chip and effective methodologies of removing the heat from the system has become the order of the day. Thermoelectric (TE) devices have shown promise for on-demand cooling of ICs. However, the additional energy required for cooling remains a challenge for the successful deployment of these devices. This thesis presents a closed loop control system that dynamically switches a TE module between Peltier and Seebeck modes depending on chip temperature. The autonomous system harvests energy during regular operation and uses the harvested energy to cool during high power operation. The system is demonstrated using a commercial thin-film TE device, an integrated boost regulator and few off chip components. The feasibility of the integration of the TEM and the automated mode switching within the microprocessor package is also evaluated. With continuous usage of thermoelectric modules, it starts to degrade over time due to thermal and mechanical induced stress which in turn reduces the cooling performance over time. Impact of thermal cycling on thermoelectric cooling performance over time is evaluated using the developed full chip package model.M.S