45 research outputs found
Automated runnable to task mapping
We propose in this paper, a method to automatically map runnables (blocks of code with dedicated functionality) with real-time constraints to tasks (or threads). We aim at reducing the number of tasks runnables are mapped to, while preserving the schedulability of the initial system. We consider independent tasks running on a single processor. Our approach has been applied with fixed-task or fixed-job priorities assigned in a Deadline Monotonic (DM) or a Earliest Deadline First (EDF) manner
AUTOSAR 기반 차량 시스템의 성능 최적화를 위한 러너블-태스크 매핑 규칙
학위논문 (석사)-- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2019. 2. 홍성수.자동차가 점차 전장화됨에 따라 차량용 소프트웨어의 크기와 복잡도가 크게 증가하고 있다. 이 때문에 차량용 소프트웨어의 개발에 소요되는 시간과 비용 또한 증가하여 유럽의 주요 자동차 회사들은 개발의 효율성을 높이고자 AUTOSAR(AUTomotive Open System ARchitecture) 표준을 제정하였다. AUTOSAR 표준은 차량용 소프트웨어의 아키텍처와 개발 과정을 정의한 표준으로써 현재 많은 자동차 회사들에서 이를 준수하여 제품을 개발하고 있다.
AUTOSAR 표준에 따른 응용 소프트웨어는 소프트웨어 컴포넌트(software component) 단위로 모듈화되어 설계되며 각각의 소프트웨어 컴포넌트는 자신의 기능을 구현하는 러너블(runnable)을 1개 이상 갖는다. 개발자는 러너블을 동작시키기 위해 운영체제의 스케줄링 단위인 태스크에 매핑하는데, 러너블-태스크 매핑에 따라 시스템 오버헤드 발생량이 크게 달라지므로 이는 시스템 성능 측면에서 매우 중요한 작업이다.
본 학위 논문에서는 자율주행을 수행하는 타겟 응용의 성능 최적화를 위해 기존 연구에서 제안한 6개의 러너블-태스크 매핑 규칙을 적용하며, 추가적인 성능 향상을 위해 기존 규칙을 개선한 매핑 규칙을 제안한다. 제안된 규칙을 적용하여 매핑했을 때와 개발자가 임의로 매핑했을 때 타겟 응용의 성능을 실험을 통해 비교하며, Infineon 사의 AURIX 보드와 ETAS 사의 AUTOSAR 플랫폼 상에서 타겟 응용을 구현하여 실험하였다. 실험 결과 제안된 규칙을 적용하여 매핑했을 때 타겟 응용의 종단 간 응답 시간(end-to-end response time)이 개발자가 임의로 매핑했을 때의 기댓값보다 약 1.49배 짧은 것으로 확인되었다.As automobiles become increasingly electric, the size and complexity of automotive software is greatly increasing. As a result, the time and cost of developing automotive software has also increased, leading European automotive companies have established the AUTOSAR (Automotive Open System Architecture) standard to improve development efficiency. The AUTOSAR standard is the standard for the architecture and development process of automotive software.
Application software according to the AUTOSAR standard is modularized in software components, and each software component has one or more runnables that implement its functions. The developer maps the runnables to the tasks, which is the scheduling unit of the operating system, in order to execute the runnable. Runnable-to-task mapping is very important process in terms of system performance, since the system overhead incurred greatly depends on the runnable-to-task mapping.
In this thesis, I apply six runnable-to-task mapping rules proposed in the previous research to optimize the performance of the target application that performs autonomous driving, and propose mapping rules that improves the existing rules for further performance enhancement. I compare the performance of the target application when the runnables are mapped to the tasks according to the proposed mapping rules and when the developer arbitrarily mapped it. The target application is implemented on the Infineon AURIX board and ETAS AUTOSAR platform. Experimental results show that the end-to-end response time of the target application when mapped by applying the proposed rules is about 1.49 times shorter than the expected value when the developer arbitrarily mapped.목 차
제 1 장 서 론 1
제 2 장 배경지식과 관련 연구 4
제 1 절 AUTOSAR 4
1.1 AUTOSAR 개괄 4
1.2 AUTOSAR의 수행 모델 7
1.3 AUTOSAR의 통신 8
제 2 절 관련 연구 10
2.1 매핑 알고리즘을 제안하는 연구 10
2.2 매핑 규칙을 제안하는 연구 11
제 3 장 러너블-태스크 매핑 규칙 12
제 1 절 6가지 매핑 규칙 설명 12
제 2 절 매핑 규칙의 개선 15
제 4 장 타겟 응용에 대한 매핑 규칙 적용 17
제 1 절 타겟 응용 설명 17
제 2 절 규칙 적용 20
2.1 기존 규칙 적용 20
2.2 개선된 규칙 적용 21
제 5 장 실험 및 검증 23
제 1 절 실험 환경 23
제 2 절 실험 구성 23
제 3 절 실험 결과 및 평가 25
제 6 장 결 론 26
참고문헌 27
Abstract 29Maste
Parallelisation efficace de larges applications temps-reel
We present a parallel compilation method for embedded control applications. The method is fully automatic and scales up, being based on low-complexity heuristics. Unlike classical compilation, it also takes as input non-functional requirements, e.g. real-time or resource limits.The main objective is not optimization per se, but the respect of requirements. To this end, static resource allocation and code generation algorithms perform a safe accounting of non-functional properties. Accounting starts from per-component time and memory footprint worst-case bounds, automatically obtained through calls to state-of-the-art static analysis tools. Experiments show that our method produces efficient code for large-scale, real-life avionics applications
Continuous integration of AUTOSAR software
Die vorliegende Masterarbeit evaluiert und optimiert ein Konzept zu Continuous Integration (CI) von AUTOSAR Software der Firma Vector Informatik GmbH. Aus der Evaluierung des Konzepts folgte, dass die manuelle Konfiguration der Runtime Environment einer AUTOSAR Software, bestehend aus den Schritten Port-Mapping und Runnable-Task-Mapping, zu Problemen bei der Umsetzung der CI-Praktiken führte. Aus diesem Grund wurde als Ziel der Arbeit eine Optimierung des Konzepts durch die Automatisierung der Konfiguration festgelegt. Dazu wurde ein Ansatz zur Automatisierung des Port-Mappings und des Runnable-Task-Mappings entwickelt, welches sowohl auf Ideen aus wissenschaftlichen Publikation als auch Industriepraktiken basiert. Darauf folgte die Implementierung des Ansatzes als eine Groovy-Applikation, um anschließend eine Evaluierung basierend auf einem aktuellen AUTOSAR Projekt durchzuführen. Die Evaluierung lieferte ein positives Ergebnis in Bezug auf das Runnable-Task-Mapping, wohingegen die Verwendung des Port-Mappings für CI nur mit Einschränkungen möglich ist.This master thesis evaluates and optimizes a Continuous Integration (CI) concept for AUTOSAR software from Vector Informatik GmbH. The evaluation of the concept has shown, that the manual configuration of the runtime environment of a AUTOSAR software, consisting of the steps of port mapping and runnable task mapping, led to problems in the implementation of CI practices. For this reason, the goal of the work was to optimize the concept by automating the configuration. For this purpose, an approach for the automation of port mapping and runnable task mapping has been developed, which is based both on ideas from scientific publications as well as on industrial practices. This was followed by the implementation of the approach as a Groovy application in order to carry out an evaluation based on a current AUTOSAR project. The evaluation yielded a positive result with respect to the runnable task mapping, whereas the use of port mapping for CI is only possible with restrictions
Embedded electronic systems driven by run-time reconfigurable hardware
Abstract
This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen
Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum
Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria
Proceedings Work-In-Progress Session of the 13th Real-Time and Embedded Technology and Applications Symposium
The Work-In-Progress session of the 13th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS\u2707) presents papers describing contributions both to state of the art and state of the practice in the broad field of real-time and embedded systems. The 17 accepted papers were selected from 19 submissions. This proceedings is also available as Washington University in St. Louis Technical Report WUCSE-2007-17, at http://www.cse.seas.wustl.edu/Research/FileDownload.asp?733. Special thanks go to the General Chairs – Steve Goddard and Steve Liu and Program Chairs - Scott Brandt and Frank Mueller for their support and guidance
Timing analysis of an embedded architecture for a real-time power line communications network
Tese de mestrado. Engenharia Electrotécnica e de Computadores (Área de especialização de Telecomunicações). Faculdade de Engenharia. Universidade do Porto, Instituto Superior de Engenharia. Instituto Politécnico do Porto.. 200
Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021
The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing
A Multi-core processor for hard real-time systems
The increasing demand for new functionalities in current and future hard real-time embedded systems, like the ones deployed in automotive and avionics industries, is driving an increment in the performance required in current embedded processors. Multi-core processors represent a good design solution to cope with such higher performance requirements due to their better performance-per-watt ratio while maintaining the core design simple. Moreover, multi-cores also allow executing mixed-criticality level workloads composed of tasks with and without hard real-time requirements, maximizing the utilization of the hardware resources while guaranteeing low cost and low power consumption.
Despite those benefits, current multi-core processors are less analyzable than single-core ones due to the interferences between different tasks when accessing hardware shared resources. As a result, estimating a meaningful Worst-Case Execution Time (WCET) estimation - i.e. to compute an upper bound of the application's execution time - becomes extremely difficult, if not even impossible, because the execution time of a task may change depending on the other threads running at the same time. This makes the WCET of a task dependent on the set of inter-task interferences introduced by the co-running tasks.
Providing a WCET estimation independent from the other tasks (time composability property) is a key requirement in hard real-time systems.
This thesis proposes a new multi-core processor design in which time composability is achieved, hence enabling the use of multi-cores in hard real-time systems. With our proposals the WCET estimation of a HRT is independent from the other co-running tasks. To that end, we design a multi-core processor in which the maximum delay a request from a Hard Real-time Task (HRT), accessing a hardware shared resource can suffer due to other tasks is bounded: our processor guarantees that a request to a shared resource cannot be delayed longer than a given Upper Bound Delay (UBD).
In addition, the UBD allows identifying the impact that different processor configurations may have on the WCET by determining the sensitivity of a HRT to different resource allocations. This thesis proposes an off-line task allocation algorithm (called IA3: Interference-Aware Allocation Algorithm), that allocates tasks in a task set based on the HRT's sensitivity to different resource allocations. As a result the hardware shared resources used by HRTs are minimized, by allowing Non Hard Real-time Tasks (NHRTs) to use the rest of resources. Overall, our proposals provide analyzability for the HRTs allowing NHRTs to be executed into the same chip without any effect on the HRTs.
The previous first two proposals of this thesis focused on supporting the execution of multi-programmed workloads with mixed-criticality levels (composed of HRTs and NHRTs).
Higher performance could be achieved by implementing multi-threaded applications. As a first step towards supporting hard real-time parallel applications, this thesis proposes a new hardware/software approach to guarantee a predictable execution of software pipelined parallel programs.
This thesis also investigates a solution to verify the timing correctness of HRTs without requiring any modification in the core design: we design a hardware unit which is interfaced with the processor and integrated into a functional-safety aware methodology. This unit monitors the execution time of a block of instructions and it detects if it exceeds the WCET. Concretely, we show how to handle timing faults on a real industrial automotive platform.La creciente demanda de nuevas funcionalidades en los sistemas empotrados de tiempo real actuales y futuros en
industrias como la automovilística y la de aviación, está impulsando un incremento en el rendimiento necesario en los
actuales procesadores empotrados. Los procesadores multi-núcleo son una solución eficiente para obtener un mayor
rendimiento ya que aumentan el rendimiento por vatio, manteniendo el diseño del núcleo simple.
Por otra parte, los procesadores multi-núcleo también permiten ejecutar cargas de trabajo con niveles de tiempo real mixtas
(formadas por tareas de tiempo real duro y laxo así como tareas sin requerimientos de tiempo real), maximizando así la
utilización de los recursos de procesador y garantizando el bajo consumo de energía.
Sin embargo, a pesar los beneficios mencionados anteriormente, los actuales procesadores multi-núcleo son menos
analizables que los de un solo núcleo debido a las interferencias surgidas cuando múltiples tareas acceden
simultáneamente a los recursos compartidos del procesador.
Como resultado, la estimación del peor tiempo de ejecución (conocido como WCET) - es decir, una cota superior del tiempo
de ejecución de la aplicación - se convierte en extremadamente difícil, si no imposible, porque el tiempo de ejecución de
una tarea puede cambiar dependiendo de las otras tareas que se estén ejecutando concurrentemente. Determinar una
estimación del WCET independiente de las otras tareas es un requisito clave en los sistemas empotrados de tiempo real
duro. Esta tesis propone un nuevo diseño de procesador multi-núcleo en el que el tiempo de ejecución de las tareas se
puede componer, lo que permitirá el uso de procesadores multi-núcleo en los sistemas de tiempo real duro. Para ello,
diseñamos un procesador multi-núcleo en el que la máxima demora que puede sufrir una petición de una tarea de tiempo
real duro (HRT) para acceder a un recurso hardware compartido debido a otras tareas está acotado, tiene un límite superior
(UBD).
Además, UBD permite identificar el impacto que las diferentes posibles configuraciones del procesador pueden tener en el
WCET, mediante la determinación de la sensibilidad en la variación del tiempo de ejecución de diferentes reservas de
recursos del procesador. Esta tesis propone un algoritmo estático de reserva de recursos (llamado IA3), que asigna tareas
a núcleos en función de dicha sensibilidad. Como resultado los recursos compartidos del procesador usados por tareas
HRT se reducen al mínimo, permitiendo que las tareas sin requerimiento de tiempo real (NHRTs) puedas beneficiarse del
resto de recursos.
Por lo tanto, las propuestas presentadas en esta tesis permiten el análisis del WCET para tareas HRT, permitiendo así
mismo la ejecución de tareas NHRTs en el mismo procesador multi-núcleo, sin que estas tengan ningún efecto sobre las
tareas HRT.
Las propuestas presentadas anteriormente se centran en el soporte a la ejecución de múltiples cargas de trabajo con
diferentes niveles de tiempo real (HRT y NHRTs).
Sin embargo, un mayor rendimiento puede lograrse mediante la transformación una tarea en múltiples sub-tareas
paralelas. Esta tesis propone una nueva técnica, con soporte del procesador y del sistema operativo, que garantiza una
ejecución analizable del modelo de ejecución paralela software pipelining.
Esta tesis también investiga una solución para verificar la corrección del WCET de HRT sin necesidad de ninguna
modificación en el diseño de la base: un nuevo componente externo al procesador se conecta a este sin necesidad de
modificarlo. Esta nueva unidad monitorea el tiempo de ejecución de un bloque de instrucciones y detecta si se excede el
WCET. Esta unidad permite detectar fallos de sincronización en sistemas de computación utilizados en automóviles