Elastic DVS Management in Processors with Discrete Voltage/Frequency Modes

Applying classical dynamic voltage scaling (DVS) techniques to real-time systems running on processors with discrete voltage/frequency modes causes a waste of computational resources. In fact, whenever the ideal speed level computed by the DVS algorithm is not available in the system, to guarantee the feasibility of the task set, the processor speed must be set to the nearest level greater than the optimal one, thus underutilizing the system. Whenever the task set allows a certain degree of flexibility in specifying timing constraints, rate adaptation techniques can be adopted to balance performance (which is a function of task rates) versus energy consumption (which is a function of the processor speed). In this paper, we propose a new method that combines discrete DVS management with elastic scheduling to fully exploit the available computational resources. Depending on the application requirements, the algorithm can be set to improve performance or reduce energy consumption, so enhancing the flexibility of the system. A reclaiming mechanism is also used to take advantage of early completions. To make the proposed approach usable in real-world applications, the task model is enhanced to consider some of the real CPU characteristics, such as discrete voltage/frequency levels, switching overhead, task execution times nonlinear with the frequency, and tasks with different power consumption. Implementation issues and experimental results for the proposed algorithm are also discussed

Online Dynamic Power Management with Hard Real-Time Guarantees

We consider the problem of online dynamic power management that provides hard real-time guarantees for multi-processor systems. In this problem, a set of jobs, each associated with an arrival time, a deadline, and an execution time, arrives to the system in an online fashion. The objective is to compute a non-migrative preemptive schedule of the jobs and a sequence of power on/off operations of the processors so as to minimize the total energy consumption while ensuring that all the deadlines of the jobs are met. We assume that we can use as many processors as necessary. In this paper we examine the complexity of this problem and provide online strategies that lead to practical energy-efficient solutions for real-time multi-processor systems. First, we consider the case for which we know in advance that the set of jobs can be scheduled feasibly on a single processor. We show that, even in this case, the competitive factor of any online algorithm is at least 2.06. On the other hand, we give a 4-competitive online algorithm that uses at most two processors. For jobs with unit execution times, the competitive factor of this algorithm improves to 3.59. Second, we relax our assumption by considering as input multiple streams of jobs, each of which can be scheduled feasibly on a single processor. We present a trade-off between the energy-efficiency of the schedule and the number of processors to be used. More specifically, for k given job streams and h processors with h>k, we give a scheduling strategy such that the energy usage is at most 4.k/(h-k) times that used by any schedule which schedules each of the k streams on a separate processor. Finally, we drop the assumptions on the input set of jobs. We show that the competitive factor of any online algorithm is at least 2.28, even for the case of unit job execution times for which we further derive an O(1)-competitive algorithm

Exploitation de la variabilité des tâches pour minimiser la consommation d'énergie sous des contraintes temps-réels

This paper proposes a Markov Decision Process (MDP) approach to compute the optimal on-line speed scaling policy that minimizes the energy consumption of a single processor executing a finite or infinite set of jobs with real-time constraints, in the non-clairvoyant case,i.e., when the actual execution time of the jobs is unknown when they are released. In real life applications, it is common at release time to know only the Worst-Case Execution Time of a job, and the actual execution time of this job is only discovered when it finishes. Choosing the processor speed purely in function of the Worst-Case Execution Time is sub-optimal. When the probability distribution of the actual execution time is known, it is possible to exploit this knowledge to choose a lower processor speed so as to minimize the expected energy consumption (while still guaranteeing that all jobs meet their deadline). Our MDP solution solves this problem optimally with discrete processor speeds. Compared with approaches from the literature, the gain offered by the new policy ranges from a few percent when the variability of job characteristics is small, tomore than 50%when the job execution time distributions are far from their worst case

Applying real-time interface and calculus for dynamic power management in hard real-time systems

Power dissipation has been an important design issue for a wide range of computer systems in the past decades. Dynamic power consumption due to signal switching activities and static power consumption due to leakage current are the two major sources of power consumption in a CMOS circuit. As CMOS technology advances towards deep sub-micron domain, static power dissipation is comparable to or even more than dynamic power dissipation. This article explores how to apply dynamic power management to reduce static power for hard real-time systems. We propose online algorithms that adaptively control the power mode of a system, procrastinating the processing of arrived events as late as possible. To cope with multiple event streams with different characteristics, we provide solutions for preemptive earliest-deadline-first and fixed-priority scheduling policies. By adopting a worst-case interval-based abstraction, our approach can not only tackle arbitrary event arrivals, e.g., with burstiness, but also guarantee hard real-time requirements with respect to both timing and backlog constraints. We also present extensive simulation results to demonstrate the effectiveness of our approache

Energy-Aware Scheduling for Streaming Applications

Streaming applications have become increasingly important and widespread,with application domains ranging from embedded devices to server systems.Traditionally, researchers have been focusing on improving the performanceof streaming applications to achieve high throughput and low response time.However, increasingly more attention is being shifted topower/performance trade-offbecause power consumption has become a limiting factor on system designas integrated circuits enter the realm of nanometer technology.This work addresses the problem of scheduling a streaming application(represented by a task graph)with the goal of minimizing its energy consumptionwhile satisfying its two quality of service (QoS) requirements,namely, throughput and response time.The available power management mechanisms are dynamic voltage scaling (DVS),which has been shown to be effective in reducing dynamic power consumption, andvary-on/vary-off, which turns processors on and off to save static power consumption.Scheduling algorithms are proposed for different computing platforms (uniprocessor and multiprocessor systems),different characteristics of workload (deterministic and stochastic workload),and different types of task graphs (singleton and general task graphs).Both continuous and discrete processor power models are considered.The highlights are a unified approach for obtaining optimal (or provably close to optimal)uniprocessor DVS schemes for various DVS strategies anda novel multiprocessor scheduling algorithm that exploits the differencebetween the two QoS requirements to perform processor allocation,task mapping, and task speedscheduling simultaneously

Memory-Aware Scheduling for Fixed Priority Hard Real-Time Computing Systems

As a major component of a computing system, memory has been a key performance and power consumption bottleneck in computer system design. While processor speeds have been kept rising dramatically, the overall computing performance improvement of the entire system is limited by how fast the memory can feed instructions/data to processing units (i.e. so-called memory wall problem). The increasing transistor density and surging access demands from a rapidly growing number of processing cores also significantly elevated the power consumption of the memory system. In addition, the interference of memory access from different applications and processing cores significantly degrade the computation predictability, which is essential to ensure timing specifications in real-time system design. The recent IC technologies (such as 3D-IC technology) and emerging data-intensive real-time applications (such as Virtual Reality/Augmented Reality, Artificial Intelligence, Internet of Things) further amplify these challenges. We believe that it is not simply desirable but necessary to adopt a joint CPU/Memory resource management framework to deal with these grave challenges. In this dissertation, we focus on studying how to schedule fixed-priority hard real-time tasks with memory impacts taken into considerations. We target on the fixed-priority real-time scheduling scheme since this is one of the most commonly used strategies for practical real-time applications. Specifically, we first develop an approach that takes into consideration not only the execution time variations with cache allocations but also the task period relationship, showing a significant improvement in the feasibility of the system. We further study the problem of how to guarantee timing constraints for hard real-time systems under CPU and memory thermal constraints. We first study the problem under an architecture model with a single core and its main memory individually packaged. We develop a thermal model that can capture the thermal interaction between the processor and memory, and incorporate the periodic resource sever model into our scheduling framework to guarantee both the timing and thermal constraints. We further extend our research to the multi-core architectures with processing cores and memory devices integrated into a single 3D platform. To our best knowledge, this is the first research that can guarantee hard deadline constraints for real-time tasks under temperature constraints for both processing cores and memory devices. Extensive simulation results demonstrate that our proposed scheduling can improve significantly the feasibility of hard real-time systems under thermal constraints

Integrated Data and Energy Communication Network: A Comprehensive Survey

OAPA In order to satisfy the power thirsty of communication devices in the imminent 5G era, wireless charging techniques have attracted much attention both from the academic and industrial communities. Although the inductive coupling and magnetic resonance based charging techniques are indeed capable of supplying energy in a wireless manner, they tend to restrict the freedom of movement. By contrast, RF signals are capable of supplying energy over distances, which are gradually inclining closer to our ultimate goal – charging anytime and anywhere. Furthermore, transmitters capable of emitting RF signals have been widely deployed, such as TV towers, cellular base stations and Wi-Fi access points. This communication infrastructure may indeed be employed also for wireless energy transfer (WET). Therefore, no extra investment in dedicated WET infrastructure is required. However, allowing RF signal based WET may impair the wireless information transfer (WIT) operating in the same spectrum. Hence, it is crucial to coordinate and balance WET and WIT for simultaneous wireless information and power transfer (SWIPT), which evolves to Integrated Data and Energy communication Networks (IDENs). To this end, a ubiquitous IDEN architecture is introduced by summarising its natural heterogeneity and by synthesising a diverse range of integrated WET and WIT scenarios. Then the inherent relationship between WET and WIT is revealed from an information theoretical perspective, which is followed by the critical appraisal of the hardware enabling techniques extracting energy from RF signals. Furthermore, the transceiver design, resource allocation and user scheduling as well as networking aspects are elaborated on. In a nutshell, this treatise can be used as a handbook for researchers and engineers, who are interested in enriching their knowledge base of IDENs and in putting this vision into practice

Software Approaches to Manage Resource Tradeoffs of Power and Energy Constrained Applications

Power and energy efficiency have become an increasingly important design metric for a wide spectrum of computing devices. Battery efficiency, which requires a mixture of energy and power efficiency, is exceedingly important especially since there have been no groundbreaking advances in battery capacity recently. The need for energy and power efficiency stretches from small embedded devices to portable computers to large scale data centers. The projected future of computing demand, referred to as exascale computing, demands that researchers find ways to perform exaFLOPs of computation at a power bound much lower than would be required by simply scaling today's standards. There is a large body of work on power and energy efficiency for a wide range of applications and at different levels of abstraction. However, there is a lack of work studying the nuances of different tradeoffs that arise when operating under a power/energy budget. Moreover, there is no work on constructing a generalized model of applications running under power/energy constraints, which allows the designer to optimize their resource consumption, be it power, energy, time, bandwidth, or space. There is need for an efficient model that can provide bounds on the optimality of an application's resource consumption, becoming a basis against which online resource management heuristics can be measured. In this thesis, we tackle the problem of managing resource tradeoffs of power/energy constrained applications. We begin by studying the nuances of power/energy tradeoffs with the response time and throughput of stream processing applications. We then study the power performance tradeoff of batch processing applications to identify a power configuration that maximizes performance under a power bound. Next, we study the tradeoff of power/energy with network bandwidth and precision. Finally, we study how to combine tradeoffs into a generalized model of applications running under resource constraints. The work in this thesis presents detailed studies of the power/energy tradeoff with response time, throughput, performance, network bandwidth, and precision of stream and batch processing applications. To that end, we present an adaptive algorithm that manages stream processing tradeoffs of response time and throughput at the CPU level. At the task-level, we present an online heuristic that adaptively distributes bounded power in a cluster to improve performance, as well as an offline approach to optimally bound performance. We demonstrate how power can be used to reduce bandwidth bottlenecks and extend our offline approach to model bandwidth tradeoffs. Moreover, we present a tool that identifies parts of a program that can be downgraded in precision with minimal impact on accuracy, and maximal impact on energy consumption. Finally, we combine all the above tradeoffs into a flexible model that is efficient to solve and allows for bounding and/or optimizing the consumption of different resources