Fabrication of micro bumps for micro scale thermal management

Cryopreservation is storage of biological systems at ultra low temperatures for a prolonged duration; such that they can be thawed and restored to the same living state. It is important to understand the behavior of cells when they are subjected to subzero temperatures. Research in this area has shown the occurrence of two main biophysical events; cellular dehydration and intracellular ice formation. Current techniques for characterizing the dehydration in cells as part of a tissue are not adequate for studying intracellular ice formation in tissues. An integrated device consisting of an array of thermal sensors (microthermocouples) and actuators (microthermoelectric coolers) would help to detect intracellular ice formation by measuring and modulating the heat release of individual cells during freezing. This requires a dense wiring layer below the devices which can act as a heat sink in turn affecting the performance of the device. To alleviate this problem fabrication of bump structures was proposed to isolate the dense wiring layer from the array. Modeling was used to assess the effect of the bumps on the performance of the thermoelectric cooler. Bismuth telluride posts of 10 µm diameter and 20 µm height yielded optimal cooling with a bump radius of 5 µm. A maximum effective change in temperature of 3.47 K was achieved for an applied current of 23.7 mA and Joule’s breakdown was found to occur at 47.7 mA. To avoid the complexities in the measurements due to the presence of second junction, copper and constantan were chosen as bump material. Electrodeposition along with UV-LIGA microfabrication technique was used to fabricate the bumps. Copper and constantan micro bumps, with mean diameters of 6.5 & 27.76 µm and heights of 7.81 and 12.04 µm were fabricated with dimensional variation of ±0.5 µm with a 95% confidence interval. A custom printed circuit board was fabricated on FR4 laminate using lithography and liftoff technique. The mean length and width of the structures were found to be 4151.98 ±1.86 µm and 1003.21 ±0.55 µm, respectively with 95% confidence interval. There is a need for future work to precisely fabricate metal features on FR4 laminate

A planar thermoelectric power generator for integration in wearable microsystems

A technique for IC-compatible fabrication of a planar (in-plane) thermoelectric (TE) power generator using a thermopile composed of n-type bismuth telluride (Bi2Te3) and p-type antimony telluride (Sb2Te3) thin-films is presented. The research demonstrates that the thermal co-evaporation of bismuth/antimony (Bi/Sb) and telluride (Te) is the most suitable deposition technique. The measurements showed TE performance properties of the deposited thin-films that are comparable to those reported for the same materials in the bulk form. The measurements showed absolute values of the Seebeck coefficient in the range 91–248 VK−1, an electrical resistivity in the 7.6–39.1 m range and a thermal conduction between 1.3 and 1.8Wm−1 K−1. The best resulting figures-of-merit, ZT, at room temperatures were 0.97 and 0.56 (equivalent to power-factors, PF, of 4.87×10−3 and 2.8×10−3WK−1m−2) for the Bi2Te3 and Sb2Te3 thin-films, respectively. The IC-compatibility and the dependence of the TE performance on technological details, such as photolithography and wet etching used for patterning the thin-films have also been investigated. The converter dimensions for best performance were analysed and a prototype of a planar TE power generator was fabricated

Pulsed laser deposition of Bismuth Telluride compounds for human body energy scavengers

The world wide research interest in Bismuth Telluride thin films is due to the fact that they are the most commonly efficient thermoelectric materials at temperatures as low as room temperature, which is typically suitable for implementing such thin films through the fabrication of miniaturized thermoelectric generators and human body energy scavengers. This work aims to characterize various Bismuth Telluride -based thin films deposited by Pulsed Laser Deposition technique in order to optimize their thermoelectric performance represented in their thermoelectric figures of merit. This has been achieved by investigating the electrical and thermoelectric properties of the deposited thin films as well as studying the structural properties of such thin films that is necessary for future micromachining and fabrication of energy scavengers; the results of this effort are really promising. The first chapter is an introductory overview concerning thermoelectric effects and thermoelectric generators. The second chapter deals with the different deposition techniques and the reasoning behind the employment of PLD to deposit Bismuth Telluride thin films. The third chapter includes some of Bismuth Telluride chemical and physical properties in addition to a literature survey of what other groups have already achieved concerning this material. The fourth chapter covers all the experiments and includes the results of this work. Finally, the fifth chapter includes the summary, conclusion and recommendation for future progress in this topic

On-Chip Thermoelectric Cooling of Semiconductor Hot Spot

The Moore's Law progression in semiconductor technology, including shrinking feature size, increasing transistor density, and faster circuit speeds, is leading to increasing total power dissipations and heat fluxes on silicon chip. Moreover, in recent years, increasing performance has resulted in greater non-uniformity of on-chip power dissipation, creating microscale hot spots that can significantly degrade the processor performance and reliability. Application of conventional thermal packaging technology, developed to provide uniform chip cooling, to such chip designs results in lower allowable chip power dissipation or overcooling of large areas of the chip. Consequently, novel thermoelectric cooler (TEC) has been proposed recently for on-chip hot spot cooling because of its unique ability to selectively cool down the localized microscale hot spot. In this dissertation the potential application of thermoelectric coolers to suppress on-chip hotspots is explored using analytical modeling, numerical simulation, and experimental techniques. Single-crystal silicon is proposed as a potential thermoelectric material due to its high Seebeck coefficient and its thermoelectric cooling performance is investigated using device-level analytical modeling. Integrated on silicon chip as an integral, on-chip thermoelectric cooler, silicon microcooler can effectively reduce the hotspot temperature and its effectiveness is investigated using analytical modeling and numerical simulation, and found to be dependent of doping concentration in silicon, electric contact resistance, hotspot size, hotspot heat flux, die thickness and microcooler size. The other novel on-chip hotspot cooling solution developed in this dissertation is to use a mini-contact enhanced TEC, where the mini-contact pad connects the silicon chip and the TEC to concentrate the thermoelectric cooling power onto a spot of top surface of the silicon chip and therefore significantly improve the hotspot cooling performance. Numerical simulation shows hotspot cooling is determined by thermal contact resistance, thermoelectric element thickness, chip thickness, etc. Package-level experiment demonstrates that spot cooling performance of such mini-contact enhanced TEC can be improved by about 100%

The design and thermal measurement of III-V integrated micro-coolers for thermal management of microwave devices

Modern high frequency electronic devices are continually becoming smaller in area but capable of generating higher RF power, thereby increasing the dissipated power density. For many microwave devices, for example the planar Gunn diode, standard thermal management may no longer be sufficient to effectively remove the increasing dissipated power. The work has looked at the design and development of an active micro-cooler, which could be fully integrated with the planar Gunn diode at wafer level as a monolithic microwave integrated circuit (MMIC). The work also resulted in the further development of novel thermal measurement techniques, using micro-particle sensors with infra-red (IR) thermal microscopy and for the first time to measure thermal profiles along the channel of the planar Gunn diode. To integrate the gallium arsenide (GaAs) based planar Gunn diode and micro-cooler, it was first necessary to design and fabricate individual GaAs based planar Gunn diodes and micro-coolers for thermal and electrical characterisation. To obtain very small area micro-coolers, superlattice structures were investigated to improve the ratio between the electrical and thermal conductivities of the micro-cooler. To measure the specific contact resistivity of the superlattice based micro-cooler contacts, the Reeves & Harrison TLM (transmission line method) was used as it included both horizontal and vertical components of the contact resistance. It was found, for the GaAs based micro-cooler, only small amounts of cooling (1 ºC. A novel approach of determining if the measured cooling temperature was due to cooling or probe loading was developed. A 1D model for the integrated micro-cooler was developed and the results indicated that when the micro-cooler was used as a cooling element in a monolithic microwave integrated circuit, the supporting substrate thickness was very important. Simulation showed to obtain cooling the substrate thickness had to be very thin (<50 μm), which may preclude the use of GaAs micro-coolers as part of a monolithic microwave integrated circuit.EPSR