61 research outputs found

    ํšŒ๋กœ์˜ 1์ฐจ์› ๋ฐฐ์น˜๋ฌธ์ œ ํ•ด๊ฒฐ์„ ์œ„ํ•œ ์ƒˆ๋กœ์šด ์ง€์—ญ์ตœ์ ํ™” ์•Œ๊ณ ๋ฆฌ์ฆ˜

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    ํ•™์œ„๋…ผ๋ฌธ(์„์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ปดํ“จํ„ฐ๊ณตํ•™๋ถ€, 2023. 2. ์ด์žฌ์ง„.Area reduction is one of the most critical objectives in semiconductor design since it improves profitability due to increasing net die per wafer. Although there exist various commercial tools, memory design requires the full custom design flow to reduce the area because the place and route (P&R) functionality in the tools are not effective in the dram design flow. Furthermore, one-dimensional (1D) layout is indispensable due to the presence of peripheral regions. Inspired by the above, we propose a new framework to minimize the wire length in the standard cells 1D layout. The framework consists of the heuristic algorithm, which efficiently places standard cells to minimize the overall wire length of a 1D unit block composed of multiple standard cells and a Clustering algorithm. Through the cooperation of three algorithms, it obtains the 26.6% improved total wire length on 502 units consisting of 3 to 98 standard cells designed by human experts.๋ฉด์  ๊ฐ์†Œ๋Š” ์›จ์ดํผ๋‹น Netdie ์ฆ๊ฐ€๋กœ ์ˆ˜์ต์„ฑ์„ ๋†’์ด๊ธฐ ๋•Œ๋ฌธ์— ๋ฐ˜๋„์ฒด ์„ค๊ณ„์—์„œ ๊ฐ€์žฅ ์ค‘์š”ํ•œ ๋ชฉํ‘œ ์ค‘ ํ•˜๋‚˜์ด๋‹ค. ASIC ์„ค๊ณ„๋ฅผ ์œ„ํ•œ ๋ฉด์  ์ตœ์ ํ™”๋ฅผ ์ง€์›ํ•˜๋Š” ๋‹ค์ˆ˜์˜ ์ƒ์—…์šฉ ํˆด์ด ์กด์žฌํ•˜์ง€๋งŒ, ๋ฉ”๋ชจ๋ฆฌ ์„ค๊ณ„ ๋ถ„์•ผ์—์„œ๋Š” Full Custom Design Flow๋ฅผ ์ด์šฉํ•ด์„œ chip์˜ ๋ฉด์ ์„ ์ค„์ด๊ณ  ์žˆ๋‹ค. ์ด๋Š” ์„ค๊ณ„ ๊ด€๋ จ ๋ฐ์ดํ„ฐ์— ๋Œ€ํ•œ ๊ณต์œ ๋ฅผ ์—„๊ฒฉํžˆ ์ œํ•œํ•˜๋Š” ๋ฉ”๋ชจ๋ฆฌ ์„ค๊ณ„ ํšŒ์‚ฌ์˜ ๋ณด์•ˆ ๊ทœ์ •์œผ๋กœ ์ธํ•ด, ์ƒ์šฉ ํˆด ์ œ์ž‘ ์—…์ฒด๊ฐ€ ๋ฉ”๋ชจ๋ฆฌ ์„ค๊ณ„ ๋ถ„์•ผ์— ๊ด€๋ จ๋œ ์ตœ์ ํ™” ํˆด์„ ๊ฐœ๋ฐœํ•˜์ง€ ๋ชปํ–ˆ์Œ์— ๊ธฐ์ธํ•œ๋‹ค. ํŠนํžˆ, ๋ฉ”๋ชจ๋ฆฌ์˜ Peripheral ์˜์—ญ์„ ์„ค๊ณ„ํ•˜๊ธฐ ์œ„ํ•ด์„œ ํ‘œ์ค€ ์…€์„ 1์ฐจ์›(1D)์œผ๋กœ ๋ฐฐ์น˜ํ•˜๋Š” ์ ˆ์ฐจ๊ฐ€ ์กด์žฌํ•˜๋Š”๋ฐ, ์ด ๋˜ํ•œ ์ง€์›ํ•˜๋Š” ํˆด์ด ์—†๋Š” ์‹ค์ •์ด๋‹ค. ์œ„์˜ ๋‚ด์šฉ์—์„œ ์˜๊ฐ์„ ๋ฐ›์•„ ํ‘œ์ค€ ์…€์˜ 1์ฐจ์› ๋ฐฐ์น˜๋ฅผ ์œ„ํ•œ ๋ ˆ์ด์•„์›ƒ์—์„œ ์™€์ด์–ด ๊ธธ์ด๋ฅผ ์ตœ์†Œํ™”ํ•˜๋Š” ์ƒˆ๋กœ์šด ํ”„๋ ˆ์ž„์›Œํฌ๋ฅผ ์ œ์•ˆํ•œ๋‹ค. ํ‘œ์ค€ ์…€์„ 1์ฐจ์›์œผ๋กœ ๋ฐฐ์น˜ํ•˜๊ธฐ ์œ„ํ•œ ํ”„๋ ˆ์ž„์›Œํฌ๋Š” ๋‹ค์Œ๊ณผ ๊ฐ™์€ ์•Œ๊ณ ๋ฆฌ์ฆ˜์œผ๋กœ ๊ตฌ์„ฑ๋˜๋Š”๋ฐ, ์—ฌ๋Ÿฌ ํ‘œ์ค€ ์…€๋กœ ๊ตฌ์„ฑ๋œ 1D ๋‹จ์œ„ ๋ธ”๋ก์˜ ์ „์ฒด ์™€์ด์–ด ๊ธธ์ด๋ฅผ ์ตœ์†Œํ™”ํ•˜๊ธฐ ์œ„ํ•ด ํ‘œ์ค€ ์…€์„ ํšจ์œจ์ ์œผ๋กœ ๋ฐฐ์น˜ํ•˜๋Š” ํœด๋ฆฌ์Šคํ‹ฑ ์•Œ๊ณ ๋ฆฌ์ฆ˜, Clustering ์•Œ๊ณ ๋ฆฌ์ฆ˜ ๋ฐ ํด๋Ÿญ ์ œ๊ฑฐ-์žฌ๊ตฌ์„ฑ ์•Œ๊ณ ๋ฆฌ์ฆ˜์ด ํ”„๋ ˆ์ž„์›Œํฌ์˜ ๊ทธ ํ•ต์‹ฌ์ด๋‹ค. ์ด ์„ธ ๊ฐ€์ง€ ์•Œ๊ณ ๋ฆฌ์ฆ˜์„ ์ ์šฉํ•จ์œผ๋กœ์จ, ์ „๋ฌธ๊ฐ€๋“ค์ด ์„ค๊ณ„ํ•œ, 3~98๊ฐœ์˜ ํ‘œ์ค€ ์…€๋กœ ๊ตฌ์„ฑ๋œ 502๊ฐœ ์œ ๋‹› ๋ธ”๋ก์˜ ์ด ์™€์ด์–ด ๊ธธ์ด๋ฅผ 27.97% ๊ฐœ์„ ํ•˜๋Š” ์„ฑ๊ณผ๋ฅผ ๋‹ฌ์„ฑํ–ˆ๋‹ค.Chapter 1. Introduction ๏ผ‘ Chapter 2. Related Work ๏ผ“ Chapter 3. Contributions ๏ผ” Chapter 4. Problem Definition ๏ผ• Chapter 5. Methodology ๏ผ— 5.1. Structure of Genetic Algorithm ๏ผ˜ 5.2 MultiStart ๏ผ™ 5.3 Greedy-K: New Local Optimization Algorithm ๏ผ™ 5.4 Clustering for 1D Placement Problems ๏ผ‘๏ผ‘ 5.5 Cell Flipping ๏ผ‘๏ผ” 5.7 DFS&BFS Initialization ๏ผ‘๏ผ• Chapter 6 Experimental Results ๏ผ‘๏ผ— 6.1 Test Environment and Condition ๏ผ‘๏ผ— 6.2 Performance of DFS&BFS Initialization ๏ผ‘๏ผ˜ 6.3 Performance of Cell Flipping ๏ผ‘๏ผ˜ 6.4 GA vs. Greedy-K vs. GA+Greedy-K ๏ผ‘๏ผ™ 6.5 Human Experts vs. Cell Flipping vs. Clustering ๏ผ’๏ผ‘ 6.6 Parallel Processing ๏ผ’๏ผ’ Chapter 7 Conclusion ๏ผ’๏ผ”์„

    Radiation Tolerant Electronics, Volume II

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    Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

    Low Power Memory/Memristor Devices and Systems

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    This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within

    SALSy: Security-Aware Layout Synthesis

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    Integrated Circuits (ICs) are the target of diverse attacks during their lifetime. Fabrication-time attacks, such as the insertion of Hardware Trojans, can give an adversary access to privileged data and/or the means to corrupt the IC's internal computation. Post-fabrication attacks, where the end-user takes a malicious role, also attempt to obtain privileged information through means such as fault injection and probing. Taking these threats into account and at the same time, this paper proposes a methodology for Security-Aware Layout Synthesis (SALSy), such that ICs can be designed with security in mind in the same manner as power-performance-area (PPA) metrics are considered today, a concept known as security closure. Furthermore, the trade-offs between PPA and security are considered and a chip is fabricated in a 65nm CMOS commercial technology for validation purposes - a feature not seen in previous research on security closure. Measurements on the fabricated ICs indicate that SALSy promotes a modest increase in power in order to achieve significantly improved security metrics

    AI/ML Algorithms and Applications in VLSI Design and Technology

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    An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

    Design Automation and Application for Emerging Reconfigurable Nanotechnologies

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    In the last few decades, two major phenomena have revolutionized the electronic industry โ€“ the ever-increasing dependence on electronic circuits and the Complementary Metal Oxide Semiconductor (CMOS) downscaling. These two phenomena have been complementing each other in a way that while electronics, in general, have demanded more computations per functional unit, CMOS downscaling has aptly supported such needs. However, while the computational demand is still rising exponentially, CMOS downscaling is reaching its physical limits. Hence, the need to explore viable emerging nanotechnologies is more imperative than ever. This thesis focuses on streamlining the existing design automation techniques for a class of emerging reconfigurable nanotechnologies. Transistors based on this technology exhibit duality in conduction, i.e. they can be configured dynamically either as a p-type or an n-type device on the application of an external bias. Owing to this dynamic reconfiguration, these transistors are also referred to as Reconfigurable Field-Effect Transistors (RFETs). Exploring and developing new technologies just like CMOS, require tackling two main challenges โ€“ first, design automation flow has to be modified to enable tailor- made circuit designs. Second, possible application opportunities should be explored where such technologies can outsmart the existing CMOS technologies. This thesis targets the above two objectives for emerging reconfigurable nanotechnologies by proposing approaches for enabling an Electronic Design Automation (EDA) flow for circuits based on RFETs and exploring hardware security as an application that exploits the transistor-level dynamic reconfiguration offered by this technology. This thesis explains the bottom-up approach adopted to propose a logic synthesis flow by identifying new logic gates and circuit design paradigms that can particularly exploit the dynamic reconfiguration offered by these novel nanotechnologies. This led to the subsequent need of finding natural Boolean logic abstraction for emerging reconfigurable nanotechnologies as it is shown that the existing abstraction of negative unate logic for CMOS technologies is sub-optimal for RFETs-based circuits. In this direction, it has been shown that duality in Boolean logic is a natural abstraction for this technology and can truly represent the duality in conduction offered by individual transistors. Finding this abstraction paved the way for defining suitable primitives and proposing various algorithms for logic synthesis and technology mapping. The following step is to explore compatible physical synthesis flow for emerging reconfigurable nanotechnologies. Using silicon nanowire-based RFETs, .lef and .lib files have been provided which can provide an end-to-end flow to generate .GDSII file for circuits exclusively based on RFETs. Additionally, new approaches have been explored to improve placement and routing for circuits based on reconfigurable nanotechnologies. It has been demonstrated how these approaches led to superior results as compared to the native flow meant for CMOS. Lastly, the unique property of transistor-level reconfiguration offered by RFETs is utilized to implement efficient Intellectual Property (IP) protection schemes against adversarial attacks. The ability to control the conduction of individual transistors can be argued as one of the impactful features of this technology and suitably fits into the paradigm of security measures. Prior security schemes based on CMOS technology often come with large overheads in terms of area, power, and delay. In contrast, RFETs-based hardware security measures such as logic locking, split manufacturing, etc. proposed in this thesis, demonstrate affordable security solutions with low overheads. Overall, this thesis lays a strong foundation for the two main objectives โ€“ design automation, and hardware security as an application, to push emerging reconfigurable nanotechnologies for commercial integration. Additionally, contributions done in this thesis are made available under open-source licenses so as to foster new research directions and collaborations.:Abstract List of Figures List of Tables 1 Introduction 1.1 What are emerging reconfigurable nanotechnologies? 1.2 Why does this technology look so promising? 1.3 Electronics Design Automation 1.4 The game of see-saw: key challenges vs benefits for emerging reconfigurable nanotechnologies 1.4.1 Abstracting ambipolarity in logic gate designs 1.4.2 Enabling electronic design automation for RFETs 1.4.3 Enhanced functionality: a suitable fit for hardware security applications 1.5 Research questions 1.6 Entire RFET-centric EDA Flow 1.7 Key Contributions and Thesis Organization 2 Preliminaries 2.1 Reconfigurable Nanotechnology 2.1.1 1D devices 2.1.2 2D devices 2.1.3 Factors favoring circuit-flexibility 2.2 Feasibility aspects of RFET technology 2.3 Logic Synthesis Preliminaries 2.3.1 Circuit Model 2.3.2 Boolean Algebra 2.3.3 Monotone Function and the property of Unateness 2.3.4 Logic Representations 3 Exploring Circuit Design Topologies for RFETs 3.1 Contributions 3.2 Organization 3.3 Related Works 3.4 Exploring design topologies for combinational circuits: functionality-enhanced logic gates 3.4.1 List of Combinational Functionality-Enhanced Logic Gates based on RFETs 3.4.2 Estimation of gate delay using the logical effort theory 3.5 Invariable design of Inverters 3.6 Sequential Circuits 3.6.1 Dual edge-triggered TSPC-based D-flip flop 3.6.2 Exploiting RFETโ€™s ambipolarity for metastability 3.7 Evaluations 3.7.1 Evaluation of combinational logic gates 3.7.2 Novel design of 1-bit ALU 3.7.3 Comparison of the sequential circuit with an equivalent CMOS-based design 3.8 Concluding remarks 4 Standard Cells and Technology Mapping 4.1 Contributions 4.2 Organization 4.3 Related Work 4.4 Standard cells based on RFETs 4.4.1 Interchangeable Pull-Up and Pull-Down Networks 4.4.2 Reconfigurable Truth-Table 4.5 Distilling standard cells 4.6 HOF-based Technology Mapping Flow for RFETs-based circuits 4.6.1 Area adjustments through inverter sharings 4.6.2 Technology Mapping Flow 4.6.3 Realizing Parameters For The Generic Library 4.6.4 Defining RFETs-based Genlib for HOF-based mapping 4.7 Experiments 4.7.1 Experiment 1: Distilling standard-cells from a benchmark suite 4.7.2 Experiment 2A: HOF-based mapping . 4.7.3 Experiment 2B: Using the distilled standard-cells during mapping 4.8 Concluding Remarks 5 Logic Synthesis with XOR-Majority Graphs 5.1 Contributions 5.2 Organization 5.3 Motivation 5.4 Background and Preliminaries 5.4.1 Terminologies 5.4.2 Self-duality in NPN classes 5.4.3 Majority logic synthesis 5.4.4 Earlier work on XMG 5.4.5 Classification of Boolean functions 5.5 Preserving Self-Duality 5.5.1 During logic synthesis 5.5.2 During versatile technology mapping 5.6 Advanced Logic synthesis techniques 5.6.1 XMG resubstitution 5.6.2 Exact XMG rewriting 5.7 Logic representation-agnostic Mapping 5.7.1 Versatile Mapper 5.7.2 Support of supergates 5.8 Creating Self-dual Benchmarks 5.9 Experiments 5.9.1 XMG-based Flow 5.9.2 Experimental Setup 5.9.3 Synthetic self-dual benchmarks 5.9.4 Cryptographic benchmark suite 5.10 Concluding remarks and future research directions 6 Physical synthesis flow and liberty generation 6.1 Contributions 6.2 Organization 6.3 Background and Related Work 6.3.1 Related Works 6.3.2 Motivation 6.4 Silicon Nanowire Reconfigurable Transistors 6.5 Layouts for Logic Gates 6.5.1 Layouts for Static Functional Logic Gates 6.5.2 Layout for Reconfigurable Logic Gate 6.6 Table Model for Silicon Nanowire RFETs 6.7 Exploring Approaches for Physical Synthesis 6.7.1 Using the Standard Place & Route Flow 6.7.2 Open-source Flow 6.7.3 Concept of Driver Cells 6.7.4 Native Approach 6.7.5 Island-based Approach 6.7.6 Utilization Factor 6.7.7 Placement of the Island on the Chip 6.8 Experiments 6.8.1 Preliminary comparison with CMOS technology 6.8.2 Evaluating different physical synthesis approaches 6.9 Results and discussions 6.9.1 Parameters Which Affect The Area 6.9.2 Use of Germanium Nanowires Channels 6.10 Concluding Remarks 7 Polymporphic Primitives for Hardware Security 7.1 Contributions 7.2 Organization 7.3 The Shift To Explore Emerging Technologies For Security 7.4 Background 7.4.1 IP protection schemes 7.4.2 Preliminaries 7.5 Security Promises 7.5.1 RFETs for logic locking (transistor-level locking) 7.5.2 RFETs for split manufacturing 7.6 Security Vulnerabilities 7.6.1 Realization of short-circuit and open-circuit scenarios in an RFET-based inverter 7.6.2 Circuit evaluation on sub-circuits 7.6.3 Reliability concerns: A consequence of short-circuit scenario 7.6.4 Implication of the proposed security vulnerability 7.7 Analytical Evaluation 7.7.1 Investigating the security promises 7.7.2 Investigating the security vulnerabilities 7.8 Concluding remarks and future research directions 8 Conclusion 8.1 Concluding Remarks 8.2 Directions for Future Work Appendices A Distilling standard-cells B RFETs-based Genlib C Layout Extraction File (.lef) for Silicon Nanowire-based RFET D Liberty (.lib) file for Silicon Nanowire-based RFET

    Custom Cell Placement Automation for Asynchronous VLSI

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    Asynchronous Very-Large-Scale-Integration (VLSI) integrated circuits have demonstrated many advantages over their synchronous counterparts, including low power consumption, elastic pipelining, robustness against manufacturing and temperature variations, etc. However, the lack of dedicated electronic design automation (EDA) tools, especially physical layout automation tools, largely limits the adoption of asynchronous circuits. Existing commercial placement tools are optimized for synchronous circuits, and require a standard cell library provided by semiconductor foundries to complete the physical design. The physical layouts of cells in this library have the same height to simplify the placement problem and the power distribution network. Although the standard cell methodology also works for asynchronous designs, the performance is inferior compared with counterparts designed using the full-custom design methodology. To tackle this challenge, we propose a gridded cell layout methodology for asynchronous circuits, in which the cell height and cell width can be any integer multiple of two grid values. The gridded cell approach combines the shape regularity of standard cells with the size flexibility of full-custom layouts. Therefore, this approach can achieve a better space utilization ratio and lower wire length for asynchronous designs. Experiments have shown that the gridded cell placement approach reduces area without impacting the routability. We have also used this placer to tape out a chip in a 65nm process technology, demonstrating that our placer generates design-rule clean results
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