8,285 research outputs found

    Survey on Combinatorial Register Allocation and Instruction Scheduling

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    Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating efficient assembly code in a compiler. In the last three decades, combinatorial optimization has emerged as an alternative to traditional, heuristic algorithms for these two tasks. Combinatorial optimization approaches can deliver optimal solutions according to a model, can precisely capture trade-offs between conflicting decisions, and are more flexible at the expense of increased compilation time. This paper provides an exhaustive literature review and a classification of combinatorial optimization approaches to register allocation and instruction scheduling, with a focus on the techniques that are most applied in this context: integer programming, constraint programming, partitioned Boolean quadratic programming, and enumeration. Researchers in compilers and combinatorial optimization can benefit from identifying developments, trends, and challenges in the area; compiler practitioners may discern opportunities and grasp the potential benefit of applying combinatorial optimization

    A mathematical formulation of the loop pipelining problem

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    This paper presents a mathematical model for the loop pipelining problem that considers several parameters for optimization and supports any combination of resource and timing constraints. The unrolling degree of the loop is one of the variables explored by the model. By using Farey’s series, an optimal exploration of the unrolling degree is performed and optimal solutions not considered by other methods are obtained. Finding an optimal schedule that minimizes resource and register requirements is solved by using an Integer linear programming (ILP) model. A novel paradigm called branch and prune is proposed to eficiently converge towards the optimal schedule and prune the search tree for integer solutions, thus drastically reducing the running time. This is the first formulation that combines the unrolling degree of the loop with timing and resource constraints in a mathematical model that guarantees optimal solutions.Peer ReviewedPostprint (author's final draft

    On the Implementation of GNU Prolog

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    GNU Prolog is a general-purpose implementation of the Prolog language, which distinguishes itself from most other systems by being, above all else, a native-code compiler which produces standalone executables which don't rely on any byte-code emulator or meta-interpreter. Other aspects which stand out include the explicit organization of the Prolog system as a multipass compiler, where intermediate representations are materialized, in Unix compiler tradition. GNU Prolog also includes an extensible and high-performance finite domain constraint solver, integrated with the Prolog language but implemented using independent lower-level mechanisms. This article discusses the main issues involved in designing and implementing GNU Prolog: requirements, system organization, performance and portability issues as well as its position with respect to other Prolog system implementations and the ISO standardization initiative.Comment: 30 pages, 3 figures, To appear in Theory and Practice of Logic Programming (TPLP); Keywords: Prolog, logic programming system, GNU, ISO, WAM, native code compilation, Finite Domain constraint

    Modulo scheduling with reduced register pressure

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    Software pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Module scheduling refers to a class of algorithms for software pipelining. Most previous research on module scheduling has focused on reducing the number of cycles between the initiation of consecutive iterations (which is termed II) but has not considered the effect of the register pressure of the produced schedules. The register pressure increases as the instruction level parallelism increases. When the register requirements of a schedule are higher than the available number of registers, the loop must be rescheduled perhaps with a higher II. Therefore, the register pressure has an important impact on the performance of a schedule. This paper presents a novel heuristic module scheduling strategy that tries to generate schedules with the lowest II, and, from all the possible schedules with such II, it tries to select that with the lowest register requirements. The proposed method has been implemented in an experimental compiler and has been tested for the Perfect Club benchmarks. The results show that the proposed method achieves an optimal II for at least 97.5 percent of the loops and its compilation time is comparable to a conventional top-down approach, whereas the register requirements are lower. In addition, the proposed method is compared with some other existing methods. The results indicate that the proposed method performs better than other heuristic methods and almost as well as linear programming methods, which obtain optimal solutions but are impractical for product compilers because their computing cost grows exponentially with the number of operations in the loop body.Peer ReviewedPostprint (published version

    Breaking Instance-Independent Symmetries In Exact Graph Coloring

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    Code optimization and high level synthesis can be posed as constraint satisfaction and optimization problems, such as graph coloring used in register allocation. Graph coloring is also used to model more traditional CSPs relevant to AI, such as planning, time-tabling and scheduling. Provably optimal solutions may be desirable for commercial and defense applications. Additionally, for applications such as register allocation and code optimization, naturally-occurring instances of graph coloring are often small and can be solved optimally. A recent wave of improvements in algorithms for Boolean satisfiability (SAT) and 0-1 Integer Linear Programming (ILP) suggests generic problem-reduction methods, rather than problem-specific heuristics, because (1) heuristics may be upset by new constraints, (2) heuristics tend to ignore structure, and (3) many relevant problems are provably inapproximable. Problem reductions often lead to highly symmetric SAT instances, and symmetries are known to slow down SAT solvers. In this work, we compare several avenues for symmetry breaking, in particular when certain kinds of symmetry are present in all generated instances. Our focus on reducing CSPs to SAT allows us to leverage recent dramatic improvement in SAT solvers and automatically benefit from future progress. We can use a variety of black-box SAT solvers without modifying their source code because our symmetry-breaking techniques are static, i.e., we detect symmetries and add symmetry breaking predicates (SBPs) during pre-processing. An important result of our work is that among the types of instance-independent SBPs we studied and their combinations, the simplest and least complete constructions are the most effective. Our experiments also clearly indicate that instance-independent symmetries should mostly be processed together with instance-specific symmetries rather than at the specification level, contrary to what has been suggested in the literature

    Approaches to integrated strategic/tactical forest planning

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    Traditionally forest planning is divided into a hierarchy of planning phases. Strategic planning is conducted to make decisions about sustainable harvest levels while taking into account legislation and policy issues. Within the frame of the strategic plan, the purpose of tactical planning is to schedule harvest operations to specific areas in the immediate few years and on a finer time scale than in the strategic plan. The operative phase focuses on scheduling harvest crews on a monthly or weekly basis, truck scheduling and choosing bucking instructions. Decisions at each level are to a varying degree supported by computerized tools. A problem that may arise when planning is divided into levels and that is noted in the literature focusing on decision support tools is that solutions at one level may be inconsistent with the results of another level. When moving from the strategic plan to the tactical plan, three sources of inconsistencies are often present; spatial discrepancies, temporal discrepancies and discrepancies due to different levels of constraint. The models used in the papers presented in this thesis approaches two of these discrepancies. To address the spatial discrepancies, the same spatial resolution has been used at both levels, i.e., stands. Temporal discrepancies are addressed by modelling the tactical and strategic issues simultaneously. Integrated approaches can yield large models. One way of circumventing this is to aggregate time and/or space. The first paper addresses the consequences of temporal aggregation in the strategic part of a mixed integer programming integrated strategic/tactical model. For reference, linear programming based strategic models are also used. The results of the first paper provide information on what temporal resolutions could be used and indicate that outputs from strategic and integrated plans are not particularly affected by the number of equal length strategic periods when more than five periods, i.e. about 20 year period length, are used. The approach used in the first paper could produce models that are very large, and the second paper provides a two-stage procedure that can reduce the number of variables and preserve the allocation of stands to the first 10 years provided by a linear programming based strategic plan, while concentrating tactical harvest activities using a penalty concept in a mixed integer programming formulation. Results show that it is possible to use the approach to concentrate harvest activities at the tactical level in a full scale forest management scenario. In the case study, the effects of concentration on strategic outputs were small, and the number of harvest tracts declined towards a minimum level. Furthermore, the discrepancies between the two planning levels were small
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