Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders

This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full adders, the relative-timing assumption becomes necessary and the inherent advantages of the relative-timed RCA are: (1) computation with valid inputs, i.e., forward latency is data-dependent, and (2) computation with spacer inputs involves a bare minimum constant reverse latency of just one full adder delay, thus resulting in the optimal cycle time. With respect to different 32-bit RCA implementations, and in comparison with the optimized strong-indication, weak-indication, and early output full adder designs, one of the proposed early output full adders achieves respective reductions in latency by 67.8, 12.3 and 6.1 %, while the other proposed early output full adder achieves corresponding reductions in area by 32.6, 24.6 and 6.9 %, with practically no power penalty. Further, the proposed early output full adders based asynchronous RCAs enable minimum reductions in cycle time by 83.4, 15, and 8.8 % when considering carry-propagation over the entire RCA width of 32-bits, and maximum reductions in cycle time by 97.5, 27.4, and 22.4 % for the consideration of a typical carry chain length of 4 full adder stages, when compared to the least of the cycle time estimates of various strong-indication, weak-indication, and early output asynchronous RCAs of similar size. All the asynchronous full adders and RCAs were realized using standard cells in a semi-custom design fashion based on a 32/28 nm CMOS process technology

Asynchronous techniques for system-on-chip design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed

A Bidirectional Soft-Switched DAB-Based Single-Stage Three-Phase AC–DC Converter for V2G Application

In vehicle-to-grid applications, the battery charger of the electric vehicle (EV) needs to have a bidirectional power flow capability. Galvanic isolation is necessary for safety. An ac-dc bidirectional power converter with high-frequency isolation results in high power density, a key requirement for an on-board charger of an EV. Dual-active-bridge (DAB) converters are preferred in medium power and high voltage isolated dc-dc converters due to high power density and better efficiency. This paper presents a DAB-based three-phase ac-dc isolated converter with a novel modulation strategy that results in: 1) single-stage power conversion with no electrolytic capacitor, improving the reliability and power density; 2) open-loop power factor correction; 3) soft-switching of all semiconductor devices; and 4) a simple linear relationship between the control variable and the transferred active power. This paper presents a detailed analysis of the proposed operation, along with simulation results and experimental verification

High-Performance Architecture for Binary-Tree-Based Finite State Machines

A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer networks, compression, automatic control, or cryptography. This paper presents a new architecture for implementing BT-FSMs which is based on the model finite virtual state machine (FVSM). The proposed architecture has been compared with the general FVSM and conventional approaches by using both synthetic test benches and very large BT-FSMs obtained from a real application. In synthetic test benches, the average speed improvement of the proposed architecture respect to the best results of the other approaches achieves 41% (there are some cases in which the speed is more than double). In the case of the real application, the average speed improvement achieves 155%

The dressed atom as binary phase modulator: towards attojoule/edge optical phase-shift keying

Nanophotonic technologies offer great promise for ultra-low power optical signal processing, but relatively few nonlinear-optical phenomena have yet been explored as bases for robust digital modulation/switching~\cite{Yang07,Fara08,Liu10,Noza10}. Here we show that a single two-level system (TLS) coupled strongly to an optical resonator can impart binary phase modulation on a saturating probe beam. Our experiment relies on spontaneous emission to induce occasional transitions between positive and negative phase shifts---with each such edge corresponding to a dissipated energy of just one photon ($\approx 0.23$ aJ)---but an optical control beam could be used to trigger additional phase switching at signalling rates above this background. Although our ability to demonstrate controlled switching in our atom-based experiment is limited, we discuss prospects for exploiting analogous physics in a nanophotonic device incorporating a quantum dot as the TLS to realize deterministic binary phase modulation with control power in the aJ/edge regime.Comment: 7 pages, 4 figure