Standalone and Non-Standalone Beam Management for 3GPP NR at mmWaves

The next generation of cellular networks will exploit mmWave frequencies to dramatically increase the network capacity. The communication at such high frequencies, however, requires directionality to compensate the increase in propagation loss. Users and base stations need to align their beams during both initial access and data transmissions, to ensure the maximum gain is reached. The accuracy of the beam selection, and the delay in updating the beam pair or performing initial access, impact the end-to-end performance and the quality of service. In this paper we will present the beam management procedures that 3GPP has included in the NR specifications, focusing on the different operations that can be performed in Standalone (SA) and in Non-Standalone (NSA) deployments. We will also provide a performance comparison among different schemes, along with design insights on the most important parameters related to beam management frameworks.Comment: 7 pages, 5 figures, 1 table. Please cite it as M. Giordani, M. Polese, A. Roy, D. Castor and M. Zorzi, "Standalone and Non-Standalone Beam Management for 3GPP NR at mmWaves," in IEEE Communications Magazine, vol. 57, no. 4, pp. 123-129, April 201

A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks

The broad need to efficiently access all the instrumentation embedded within a semiconductor device called for a standardization, and the reconfigurable scan networks proposed in IEEE 1687 have been demonstrated effective in handling complex infrastructures. At the same time, different techniques have been proposed to test the new circuitry required; however, most of the automatic approaches are either too computationally demanding to be applied in complex cases, or too approximate to yield high-quality tests. This paper models the state of a reconfigurable scan network with a finite state automaton, using the length of the active path as the output alphabet and the configurations as input symbols. Permanent faults are represented as incorrect transitions, and a greedy algorithm is used to generate a functional test sequence able to detect all these multiple state-transition faults. The automaton’s state set and the input alphabet are small subsets of the possible ones, and are carefully chosen. Experimental results on ITC’16 benchmarks demonstrate that the proposed approach is broadly applicable; the test sequences are more efficient than the ones previously generated by search heuristics

Infrastructures and Algorithms for Testable and Dependable Systems-on-a-Chip

Every new node of semiconductor technologies provides further miniaturization and higher performances, increasing the number of advanced functions that electronic products can offer. Silicon area is now so cheap that industries can integrate in a single chip usually referred to as System-on-Chip (SoC), all the components and functions that historically were placed on a hardware board. Although adding such advanced functionality can benefit users, the manufacturing process is becoming finer and denser, making chips more susceptible to defects. Today’s very deep-submicron semiconductor technologies (0.13 micron and below) have reached susceptibility levels that put conventional semiconductor manufacturing at an impasse. Being able to rapidly develop, manufacture, test, diagnose and verify such complex new chips and products is crucial for the continued success of our economy at-large. This trend is expected to continue at least for the next ten years making possible the design and production of 100 million transistor chips. To speed up the research, the National Technology Roadmap for Semiconductors identified in 1997 a number of major hurdles to be overcome. Some of these hurdles are related to test and dependability. Test is one of the most critical tasks in the semiconductor production process where Integrated Circuits (ICs) are tested several times starting from the wafer probing to the end of production test. Test is not only necessary to assure fault free devices but it also plays a key role in analyzing defects in the manufacturing process. This last point has high relevance since increasing time-to-market pressure on semiconductor fabrication often forces foundries to start volume production on a given semiconductor technology node before reaching the defect densities, and hence yield levels, traditionally obtained at that stage. The feedback derived from test is the only way to analyze and isolate many of the defects in today’s processes and to increase process’s yield. With the increasing need of high quality electronic products, at each new physical assembly level, such as board and system assembly, test is used for debugging, diagnosing and repairing the sub-assemblies in their new environment. Similarly, the increasing reliability, availability and serviceability requirements, lead the users of high-end products performing periodic tests in the field throughout the full life cycle. To allow advancements in each one of the above scaling trends, fundamental changes are expected to emerge in different Integrated Circuits (ICs) realization disciplines such as IC design, packaging and silicon process. These changes have a direct impact on test methods, tools and equipment. Conventional test equipment and methodologies will be inadequate to assure high quality levels. On chip specialized block dedicated to test, usually referred to as Infrastructure IP (Intellectual Property), need to be developed and included in the new complex designs to assure that new chips will be adequately tested, diagnosed, measured, debugged and even sometimes repaired. In this thesis, some of the scaling trends in designing new complex SoCs will be analyzed one at a time, observing their implications on test and identifying the key hurdles/challenges to be addressed. The goal of the remaining of the thesis is the presentation of possible solutions. It is not sufficient to address just one of the challenges; all must be met at the same time to fulfill the market requirements

A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks

With the complexity of nanoelectronic devices rapidly increasing, an efficient way to handle large number of embedded instruments became a necessity. The IEEE 1687 standard was introduced to provide flexibility in accessing and controlling such instrumentation through a reconfigurable scan chain. Nowadays, together with testing the system for defects that may affect the scan chains themselves, the diagnosis of such faults is also important. This article proposes a method for generating stimuli to precisely identify permanent high-level faults in a IEEE 1687 reconfigurable scan chain: the system is modeled as a finite state automaton where faults correspond to multiple incorrect transitions; then, a dynamic greedy algorithm is used to select a sequence of inputs able to distinguish between all possible faults. Experimental results on the widely-adopted ITC'02 and ITC'16 benchmark suites, as well as on synthetically generated circuits, clearly demonstrate the applicability and effectiveness of the proposed approach: generated sequences are two orders of magnitude shorter compared to previous methodologies, while the computational resources required remain acceptable even for larger benchmarks

Scanning Thickness Measurement System

As technology evolves products are designed with narrower manufacturing tolerances which require more precise manufacturing practices and testing. This project designs and implements a scanning thickness gauge for use in the sheet extrusion industry. The report discusses the need for the scanning thickness gauge and why a commercially available system was not an option. The report details the steps taken to program, interface, and implement a scanning thickness gauge using an existing thickness measurement device. The finished project is discussed including the limitations of the system and future improvements to the system

A New Technique to Generate Test Sequences for Reconfigurable Scan Networks

Nowadays, industries require reliable methods for accessing the instrumentations embedded within semiconductor devices. The situation led to the definition of standards, such as the IEEE 1687, for designing the required infrastructures, and the proposal of techniques to test them. So far, most of the test-generation approaches are either too computationally demanding to be applied in complex cases, or too approximate to yield high-quality tests. This paper exploits a recent idea: the state of a generic reconfigurable scan chain is modeled as a finite state automaton and a low-level fault, as an incorrect transition; it then proposes a new algorithm for generating a functional test sequence able to detect all incorrect transitions far more efficiently than previous ones. Such an algorithm is based on a greedy search, and it is able to postpone costly operations and eventually minimize their number. Experimental results on ITC’16 benchmarks demonstrate that the proposed approach is broadly applicable; has limited computational requirements; and the test sequences are order of magnitudes shorter than the ones previously generated by approximate methodologies

A low-cost desktop software defined radio design environment using MATLAB, simulink, and the RTL-SDR

In the last 5 years, the availability of powerful DSP and Communications design software, and the emergence of relatively affordable devices that receive and digitize RF signals, has brought Software Defined Radio (SDR) to the desktops of many communications engineers. However, the more recent availability of very low cost SDR devices such as the RTL-SDR, costing less than $20, brings SDR to the home desktop of undergraduate and graduate students, as well as both professional engineers and the maker communities. Since the release of the various open source drivers for the RTL-SDR, many in the digital communications community have used this device to scan the RF spectrum and digitise I/Q signals that are being transmitted in the range 25MHz to 1.75GHz. This wide bandwidth enables the sampling of frequency bands containing signals such as FM radio, ISM signals, GSM, 3G and LTE mobile radio, GPS and so on. In this paper we will describe the opportunity and operation of the RTL-SDR, and the development of a hands-on, open-course for SDR. These educational materials can be integrated into core curriculum undergraduate and graduate courses, and will greatly enhance the teaching of DSP and communications theory, principles and applications. The lab and teaching materials have recently been used in Senior (4th year Undergraduate) courses and are available as open course materials for all to access, use and evolve