1,675 research outputs found

    Optimal 2-D cell layout with integrated transistor folding

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    ABSTRACT Folding, a key requirement in high-performance cell layout, implies breaking a large transistor into smaller, equal-sized transistors (legs) that are connected in parallel and placed contiguously with diffusion sharing. We present a novel technique FCLIP that integrates folding into the generation of optimal layouts of CMOS cells in the twodimensional (2-D) style. FCLIP is based on integer linear programming (ILP) and precisely formulates cell width minimization as a 0-1 optimization problem. Folding is incorporated into the 0-1 ILP model by variables that represent the degrees of freedom that folding introduces into cell layout. FCLIP yields optimal results for three reasons: (1) it implicitly explores all possible transistor placements; (2) it considers all diffusion sharing possibilities among folded transistors; and (3) when paired P and N transistors have unequal numbers of legs, it considers all their relative positions. FCLIP is shown to be practical for relatively large circuits with up to 30 transistors. We then extend FCLIP to accommodate and-stack clustering, a requirement in most practical designs due to its benefits on circuit performance. This reduces run times dramatically, making FCLIP viable for much larger circuits. It also demonstrates the versatility of FCLIP's ILP-based approach in easily accommodating additional design constraints. INTRODUCTION Cell layout synthesis falls in the category of constrained optimization whose goal is to find a solution that optimizes some cost function under a set of constraints. The cost function can be the cell area, its delay, or a combination of these. The constraints include bounds on width or height, aspect ratio, number of diffusion rows, or the maximum size of transistors. Since cell layout optimization is NP-hard [3], any exact algorithm can, in the worst case, have an exponential run time. Therefore, most prior techniques for cell synthesis have avoided optimal algorithms in favor of faster, but less exact heuristic methods. Maziasz and Hayes FCLIP minimizes cell area in the following stages: First, transistors are folded based on user-specified limits on the maximum size of the P and N transistors. The input circuit is preprocessed to generate P/N pairs and identify and-stacks, that is, transistors that are connected in series. And-stack clustering is not only necessary in practical designs, but also reduces the complexity of the problem and, in turn, FCLIP's run times. Then an ILP model is formulated and solved to determine a 2-D layout of minimum width W min ; this model maximizes diffusion sharing among folded transistors and minimizes vertical inter-row connections. A second ILP model is then constructed to generate a layout that has width W min and minimum height, measured by the number of horizontal routing tracks. This paper only discusses 2-D cell width minimization with folding; however, FCLIP can be extended to minimize cell height also. FCLIP yields optimal results with folding for two reasons: (1) It implicitly explores all diffusion sharing possibilities among folded transistors; and (2) when paired P/N transistors have unequal numbers of legs, it considers all their relative positions. Not only does FCLIP support 2-D layout, it is superior to prior folding techniques proposed for 1-D layou

    Standard Transistor Array (STAR). Volume 1: Placement technique

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    A large scale integration (LSI) technology, the standard transistor array uses a prefabricated understructure of transistors and a comprehensive library of digital logic cells to allow efficient fabrication of semicustom digital LSI circuits. The cell placement technique for this technology involves formation of a one dimensional cell layout and "folding" of the one dimensional placement onto the chip. It was found that, by use of various folding methods, high quality chip layouts can be achieved. Methods developed to measure of the "goodness" of the generated placements include efficient means for estimating channel usage requirements and for via counting. The placement and rating techniques were incorporated into a placement program (CAPSTAR). By means of repetitive use of the folding methods and simple placement improvement strategies, this program provides near optimum placements in a reasonable amount of time. The program was tested on several typical LSI circuits to provide performance comparisons both with respect to input parameters and with respect to the performance of other placement techniques. The results of this testing indicate that near optimum placements can be achieved by use of the procedures incurring severe time penalties

    Transistor-Level Layout of Integrated Circuits

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    In this dissertation, we present the toolchain BonnCell and its underlying algorithms. It has been developed in close cooperation with the IBM Corporation and automatically generates the geometry for functional groups of 2 to approximately 50 transistors. Its input consists of a set of transistors, including properties like their sizes and their types, a specification of their connectivity, and parameters to flexibly control the technological framework as well as the algorithms' behavior. Using this data, the tool computes a detailed geometric realization of the circuit as polygonal shapes on 16 layers. To this end, a placement routine configures the transistors and arranges them in the plane, which is the main subject of this thesis. Subsequently, a routing engine determines wires connecting the transistors to ensure the circuit's desired functionality. We propose and analyze a family of algorithms that arranges sets of transistors in the plane such that a multi-criteria target function is optimized. The primary goal is to obtain solutions that are as compact as possible because chip area is a valuable resource in modern techologies. In addition to the core algorithms we formulate variants that handle particularly structured instances in a suitable way. We will show that for 90% of the instances in a representative test bed provided by IBM, BonnCell succeeds to generate fully functional layouts including the placement of the transistors and a routing of their interconnections. Moreover, BonnCell is in wide use within IBM's groups that are concerned with transistor-level layout - a task that has been performed manually before our automation was available. Beyond the processing of isolated test cases, two large-scale examples for applications of the tool in the industry will be presented: On the one hand the initial design phase of a large SRAM unit required only half of the expected 3 month period, on the other hand BonnCell could provide valuable input aiding central decisions in the early concept phase of the new 14 nm technology generation

    GM : a gate matrix layout generator

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    The predictor-adaptor paradigm : automation of custom layout by flexible design

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    Algorithms for Cell Layout

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    Cell layout is a critical step in the design process of computer chips. A cell is a logic function or storage element implemented in CMOS technology by transistors connected with wires. As each cell is used many times on a chip, improvements of a single cell layout can have a large effect on the overall chip performance. In the past years increasing difficulty to manufacture small feature sizes has lead to growing complexity of design rules. Producing cell layouts which are compliant with design rules and at the same time optimized w.r.t. layout size has become a difficult task for human experts. In this thesis we present BonnCell, a cell layout generator which is able to fully automatically produce design rule compliant layouts. It is able to guarantee area minimality of its layouts for small and medium sized cells. For large cells it uses a heuristic which produces layouts with a significant area reduction compared to those created manually. The routing problem is based on the Vertex Disjoint Steiner Tree Packing Problem with a large number of additional design rules. In Chapter 4 we present the routing algorithm which is based on a mixed integer programming (MIP) formulation that guarantees compliance with all design rules. The algorithm can also handle instances in which only part of the transistors are placed to check whether this partial placement can be extended to a routable placement of all transistors. Chapter 5 contains the transistor placement algorithm. Based on a branch and bound approach, it places transistors in turn and achieves efficiency by pruning parts of the search tree which do not contain optimum solutions. One major contribution of this thesis is that BonnCell only outputs routable placements. Simply checking the routability for each full placement in the search tree is too slow in practice, therefore several speedup strategies are applied. Some cells are too large to be solved by a single call of the placement algorithm. In Chapter 7 we describe how these cells are split up into smaller subcells which are placed and routed individually and subsequently merged into a placement and routing of the original cell. Two approaches for dividing the original cell into subcells are presented, one based on estimating the subcell area and the other based on solving the Min Cut Linear Arrangement Problem. BonnCell has enabled our cooperation partner IBM to drastically improve their cell design and layout process. In particular, a team of human experts needed several weeks to find a layout for their largest cell, consisting of 128 transistors. BonnCell processed this cell without manual intervention in 3 days and its layout uses 15% less area than the layout found by the human experts
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