Optically Injected Circuits in a 0.18 μm CMOS

Power consumption and power conversion efficiency have been two key parameters characterizing the performance of electronic circuits since their dawn. With the increasing demand of miniaturization, mobility and portability of electronic industrial and consumer equipment, low-power and high-efficiency circuits are in high demand. Possible energy sources to enable mobility and/or portability are chemical (e.g. batteries, accumulators, micro gas, engine, fuel cells), mechanical (e.g. elastic energy in springs, vibrations, oscillations, ultrasound), thermal (e.g. body heat), EM-Field (e.g. inductive coupling, capacitive coupling, RF) and optical (photovoltaic cells). They are a great number of applications for which lowpower operation can be replaced with remote-powered operation. For optically remote powered operation, we propose the use of optically injected circuits. This has the following advantages: no need for off-chip photovoltaic cells, i.e., reduced package complexity, no need for DC-to- DC converters, i.e., improved conversion efficiency, no need for a power distribution grid, i.e., no Joules losses, and reduced interconnection complexity. This paper studies the concept of optically injected logic circuits and proposes their implementation in deep submicron and beyond CMOS technologies. This paper includes all the calculations and all the processes to fabricate the digital logic circuits. These logic circuits can be used in embedded micro-controllers where very low power operation can be replaced by remote powered operation. No local power source of any kind is necessary. Specific areas of application are data acquisition and control systems in bio-medical implants, space applications, wireless fabrication facilities and wafer-scale robots

Biosensing by “Growing” Antennas and Error-correcting Codes

Food-borne disease outbreaks not only cause numerous fatalities every year but also contribute to significant economic losses. While end-to-end supply chain monitoring can be one of the keys to preventing these outbreaks, screening every food product in the supply chain is not feasible considering the sheer volume and prohibitive test costs. Fortunately, two converging economic trends promise to make this end-to-end supply chain monitoring possible. The first trend is that passive radio-frequency identification (RFID) tags and quick response (QR) codes are now widely accepted for food packaging. The second trend is that smartphones are now equipped with the capability to interrogate RFID tags or to decode QR codes. Together, they have opened up the possibility of monitoring food quality by endowing these tags and error-correcting codes with the capability to detect pathogenic contaminants. This dissertation investigates a biosensing paradigm of growing\u27\u27 transducer structures, such as RFID tags and QR codes, which is triggered only when analytes of interest are present in the sample. This transducer growth or self-assembly process relies on a silver enhancement technique through which silver ions reduce into metallic form in the presence of a target analyte, which in turn leads to changes in electrical or optical properties. By exploiting this, we first demonstrate two remote biosensor platforms, a RFID tag-based biosensor and a QR code-based biosensor, respectively. For the RFID-based biosensor, a chain of silver-shelled particles is assembled during the analyte detection process, which directly modulates the antenna\u27s effective impedance, and hence leads to an improvement in the tag\u27s reflection efficiency. For the QR code-based biosensor, the operating principle relies on the optical absorption changes resulting from silver enhancement. The target detection process assembles an invalid code-word into a valid QR code. This self-assembly sensing approach should produce few false positives since it is a process which transits from a high entropy state (disassembled transducer) to a low entropy state (assembled transducer). While there can be numerous states of a disassembled transducer structure, there are only a few configurations representing the assembled transducer state. Given that there are no active power sources on the RFID tag or the QR code, it is challenging for the proposed biosensors to perform sample acquisition and pre-processing since they are envisioned to be embedded inside food packages eventually. Paper-based microfluidics have been explored and integrated on the biosensors to provide a self-powered approach for reagent sampling and processing. One use case is to trigger target detection remotely by an end consumer. Thermal absorption properties of graphite have been exploited such that the end user can initiate the process of analyte sampling in paper-based biosensors by shining a beam of light on the sensor

Optically-Connected Memory: Architectures and Experimental Characterizations

Growing demands on future data centers and high-performance computing systems are driving the development of processor-memory interconnects with greater performance and flexibility than can be provided by existing electronic interconnects. A redesign of the systems' memory devices and architectures will be essential to enabling high-bandwidth, low-latency, resilient, energy-efficient memory systems that can meet the challenges of exascale systems and beyond. By leveraging an optics-based approach, this thesis presents the design and implementation of an optically-connected memory system that exploits both the bandwidth density and distance-independent energy dissipation of photonic transceivers, in combination with the flexibility and scalability offered by optical networks. By replacing the electronic memory bus with an optical interconnection network, novel memory architectures can be created that are otherwise infeasible. With remote optically-connected memory nodes accessible to processors as if they are local, programming models can be designed to utilize and efficiently share greater amounts of data. Processors that would otherwise be idle, being starved for data while waiting for scarce memory resources, can instead operate at high utilizations, leading to drastic improvements in the overall system performance. This work presents a prototype optically-connected memory module and a custom processor-based optical-network-aware memory controller that communicate transparently and all-optically across an optical interconnection network. The memory modules and controller are optimized to facilitate memory accesses across the optical network using a packet-switched, circuit-switched, or hybrid packet-and-circuit-switched approach. The novel memory controller is experimentally demonstrated to be compatible with existing processor-memory access protocols, with the memory controller acting as the optics-computing interface to render the optical network transparent. Additionally, the flexibility of the optical network enables additional performance benefits including increased memory bandwidth through optical multicasting. This optically-connected architecture can further enable more resilient memory system realizations by expanding on current error dectection and correction memory protocols. The integration of optics with memory technology constitutes a critical step for both optics and computing. The scalability challenges facing main memory systems today, especially concerning bandwidth and power consumption, complement well with the strengths of optical communications-based systems. Additionally, ongoing efforts focused on developing low-cost optical components and subsystems that are suitable for computing environments may benefit from the high-volume memory market. This work therefore takes the first step in merging the areas of optics and memory, developing the necessary architectures and protocols to interface the two technologies, and demonstrating potential benefits while identifying areas for future work. Future computing systems will undoubtedly benefit from this work through the deployment of high-performance, flexible, energy-efficient optically-connected memory architectures

Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes

Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. The bidirectional interface systems have been adopted for many applications. Neuroscientists employ them to map neuronal circuits through precise stimulation and recording. Medical doctors deploy them as adaptable medical devices which control therapeutic stimulation parameters based on monitoring real-time neural activity. Brain-machine-interface (BMI) researchers use neural interfaces to bypass the nervous system and directly control neuroprosthetics or brain-computer-interface (BCI) spellers. In bidirectional interfaces, the implantable transducers as well as the corresponding electronic circuits and systems face several challenges. A high channel count, low power consumption, and reduced system size are desirable for potential chronic deployment and wider applicability. Moreover, a neural interface designed for robust closed-loop operation requires the mitigation of stimulation artifacts which corrupt the recorded signals. This dissertation introduces several techniques targeting low power consumption, small size, and reduction of stimulation artifacts. These techniques are implemented for extracellular electrophysiological recording and two stimulation modalities: direct current stimulation for closed-loop control of seizure detection/quench and optical stimulation for optogenetic studies. While the two modalities differ in their mechanisms, hardware implementation, and applications, they share many crucial system-level challenges. The first method aims at solving the critical issue of stimulation artifacts saturating the preamplifier in the recording front-end. To prevent saturation, a novel mixed-signal stimulation artifact cancellation circuit is devised to subtract the artifact before amplification and maintain the standard input range of a power-hungry preamplifier. Additional novel techniques have been also implemented to lower the noise and power consumption. A common average referencing (CAR) front-end circuit eliminates the cross-channel common mode noise by averaging and subtracting it in analog domain. A range-adapting SAR ADC saves additional power by eliminating unnecessary conversion cycles when the input signal is small. Measurements of an integrated circuit (IC) prototype demonstrate the attenuation of stimulation artifacts by up to 42 dB and cross-channel noise suppression by up to 39.8 dB. The power consumption per channel is maintained at 330 nW, while the area per channel is only 0.17 mm2. The second system implements a compact headstage for closed-loop optogenetic stimulation and electrophysiological recording. This design targets a miniaturized form factor, high channel count, and high-precision stimulation control suitable for rodent in-vivo optogenetic studies. Monolithically integrated optoelectrodes (which include 12 µLEDs for optical stimulation and 12 electrical recording sites) are combined with an off-the-shelf recording IC and a custom-designed high-precision LED driver. 32 recording and 12 stimulation channels can be individually accessed and controlled on a small headstage with dimensions of 2.16 x 2.38 x 0.35 cm and mass of 1.9 g. A third system prototype improves the optogenetic headstage prototype by furthering system integration and improving power efficiency facilitating wireless operation. The custom application-specific integrated circuit (ASIC) combines recording and stimulation channels with a power management unit, allowing the system to be powered by an ultra-light Li-ion battery. Additionally, the µLED drivers include a high-resolution arbitrary waveform generation mode for shaping of µLED current pulses to preemptively reduce artifacts. A prototype IC occupies 7.66 mm2, consumes 3.04 mW under typical operating conditions, and the optical pulse shaping scheme can attenuate stimulation artifacts by up to 3x with a Gaussian-rise pulse rise time under 1 ms.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147674/1/mendrela_1.pd

Index to NASA Tech Briefs, 1975

This index contains abstracts and four indexes--subject, personal author, originating Center, and Tech Brief number--for 1975 Tech Briefs

Roadmap on semiconductor-cell biointerfaces.

This roadmap outlines the role semiconductor-based materials play in understanding the complex biophysical dynamics at multiple length scales, as well as the design and implementation of next-generation electronic, optoelectronic, and mechanical devices for biointerfaces. The roadmap emphasizes the advantages of semiconductor building blocks in interfacing, monitoring, and manipulating the activity of biological components, and discusses the possibility of using active semiconductor-cell interfaces for discovering new signaling processes in the biological world

Towards high bandwidth communication systems: from Multi-Gbit/s over SI-POF in home scenarios to 5G cellular networks over SMF

The main objective of the thesis is to study high bandwidth communication systems for different network architectures from the end user at the in-home scenario to the service provider through the mobile cellular front-haul network. This is in parallel with the integration of power over fiber (PoF) technology in these systems.The present work received funds from the following Spanish and international projects: - Spanish Ministerio de Ciencia, Innovación y Universidades, “Tecnologías avanzadas inteligentes basadas en fibras ópticas/Advanced SMART technologies based on Optical Fibers (SMART-OF)”, grant no. RTI2018-094669-B-C32, within the coordinated project “Polymer Optical Fiber Disruptive Technologies (POFTECH)”. - Spanish Ministerio de Ciencia, Innovación y Universidades “LAboratorio de montaje, medida y CAracterización de antenas y dispositivos integrados fotónicos para comunicaciones 5G y de espacio en milimétricas, submilimétricas y THz (hasta 320 GHz) (LACA5G))”, grant no. EQC2018-005152-P. - Comunidad de Madrid “TElealimentación FotovoLtaica por fibra Óptica para medida y coNtrol en entornos extremos (TEFLON-CM)”, grant no. Y2018/EMT-4892. - Comunidad de Madrid “Sensores e Instrumentación en Tecnologías Fotónicas 2 (SINFOTON-2)”, grant no. P2018/NMT-4326, coordinated project with UC3MUPM- UAH-URCJ-CSIC. - H2020 European Union programme Bluespace project “Building the Use of Spatial Multiplexing 5G Networks Infrastructures and Showcasing Advanced Technologies and Networking Capabilities” grant nº.762055.Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Beatriz Ortega Tamarit.- Secretario: Guillermo Carpintero del Barrio.- Vocal: Óscar Esteban Martíne

High-speed low-power modulator driver arrays for medium-reach optical networks

The internet is becoming the ubiquitous tool that is changing the lives of so many citizens across the world. Commerce, government, industry, healthcare and social interactions are all increasingly using internet applications to improve and facilitate communications. This is especially true for videoenabled applications, which currently demand much higher data rates and quality from data networks. High definition TV streaming services are emerging and these again will significantly push the demand for widely deployed, high-bandwidth services. The current access passive optical networks (PONs) use a single wavelength for downstream transmission and a separate one for upstream transmission. Incorporating wavelength-division multiplexing (WDM) in a PON allows for much higher bandwidths in both directions. While WDM technologies have been successfully deployed for many years in metro and core networks, in access networks they are not commonly used yet. This is mainly due to the high costs associated with deploying entire WDM access networks. However, the present optical networks cannot be simply and cost-effectively scaled to provide the capacity for tomorrow’s users. As an effect there is a strong need for new WDM access components which are compact, cost-competitive and mass-manufacturable. Increasing the number of wavelengths for WDM-PON automatically leads to an increase in the number of single pluggable transceivers, which brings substantial design challenges and additional costs. The multitude of TXs and RXs for different wavelength channels increases the total footprint considerably. Photonic integration of transceivers into arrays will significantly reduce the footprint and cost. However, the total power consumption of an array device is an issue. To avoid the use of a thermoelectric cooler, the integration density of components is severely limited by the heat dissipating capabilities offered by their package. As a result the WDM-PON philosophy necessitates the reduction of the transceiver’s power dissipation. From this plea it is apparent that the main technology challenges for realizing future-proof optical (access) networks are reducing active component power consumption, shrinking form factors and lowering assembly costs. In this perspective an over 100 Gb/s throughput component, composed of 10 channels at 11.3 Gb/s per wavelength channel would be a great contribution to the expansion of customer bandwidth. It can provide increased line rates to the end users at speeds of 10 Gb/s per wavelength. As RXs typically consume much less power than externally modulated TXs, they can relatively easily be integrated into an array. Mainly high speed optical transmitters have significant power consumptions and the heat generation caused by power dissipation forms a critical obstacle in the development of a 10-channel transmitter, which again underlines the importance of power reduction. Alongside the introduction of WDM in access networks, also inter-office point-to-point connections in data center environments could benefit from the WDM philosophy. As data center operators often suffer from fiber scarcity or do not own their fiber infrastructure, WDM technologies are essential to deliver reach and capacity extension for these scenarios. Interdata center communication also benefits from cost-, footprint- and energyefficient components operating at high speed to maximize the throughput. As an effect integrated over 100 Gb/s transceivers, such as 4 channels at 28 Gb/s, are highly desirable. The research described in this dissertation was partly funded by the European FP7 ICT project C3PO (Colourless and Coolerless Components for low Power Optical Networks) and the UGent special research fund. The C3PO project aimed to develop a new generation of green Si-photonic compatible components with record low power consumption, that can enable bandwidth growth and constrain the total cost. C3PO envisioned building high-capacity access networks employing reflective photonic components. To achieve this, cost-competitive reflective transmitters based on electroabsorption modulators (EAM) needed to be closely integrated into arrays. A multi-wavelength optical source provides the required wavelength channels for both downstream and upstream signals in the WDM-PON. Chapter 1 gives a short overview of a PON and describes the main implementations of a WDM-PON access network. It introduces integrated low power transmitter arrays for a cost-effective architecture of WDM-PONs and inter-data center communication. Chapter 2 compares different optical transmitters and gives a short overview of their most important characteristics. External modulation through both Mach-Zehnder modulators (MZMs) and EAMs is described. It shows that EAMs are the best choice for low power transmitter array integration, thanks to their lower drive voltage and smaller form factor, compared to MZMs. To achieve a reduced consumption, the electronic modulator driver topology is studied in chapter 3. The challenge in designing modulator drivers is the need to deliver very large currents in combination with high voltage swings. Four distinct output configurations are compared and techniques to reduce the power consumption of the drivers are described. Chapter 5 presents duobinary (DB), a modulation scheme that is gaining interest in today’s optical transmission. As the required bandwidth is about half that of NRZ, it softens the constraints on the transmitter bandwidth. Thanks to its narrow optical spectrum, it has an improved tolerance to dispersion in long haul single mode links and it can improve the spectral efficiency in WDM architectures. For optical DB a precoder is necessary to assure the received signal is equal to the original binary signal. The conducted research that resulted in this dissertation produced 2 low power EAM driver arrays: A 10-channel 113 Gb/s modulator driver array with state-of-the art ultra-low power consumption. A 2-channel 56 Gb/s duobinary driver array with a differential output with low power consumption. Both designs are elaborately analyzed in chapter 4 and 6 respectively. To the best of our knowledge the 10-channel EAM driver array is the first in its kind, while achieving the lowest power consumption for an EAM driver so far reported, 50% below the state of the art in power consumption. The 2-channel EAM driver array is the fastest modulator driver including on-chip duobinary encoding and precoding reported so far. The final chapter provides an overview of the foremost conclusions from the presented research. It is concluded with suggestions for further research

System Test and Noise Performance Studies at The ATLAS Pixel Detector

The central component of the ATLAS Inner Tracker is the pixel detector. It consists of three barrel layers and three disk-layers in the endcaps in both forward directions. The innermost barrel layer is mounted at a distance of about 5~cm from the interaction region. With its very high granularity, truly two-dimensional hit information, and fast readout it is well suited to cope with the high densities of charged tracks, expected this close to the interaction region. The huge number of readout channels necessitates a very complex services infrastructure for powering, readout and safety. After a description of the pixel detector and its services infrastructure, key results from the system test at CERN are presented. Furthermore the noise performance of the pixel detector, crucial for high tracking and vertexing efficiencies, is studied. Measurements of the single-channel random noise are presented together with studies of common mode noise and measurements of the noise occupancy using a random trigger generator