Optical interconnect with densely integrated plasmonic modulator and germanium photodetector arrays

We demonstrate the first chip-to-chip interconnect utilizing a densely integrated plasmonic Mach-Zehnder modulator array operating at 3 x 10 Gbit/s. A multicore fiber provides a compact optical interface, while the receiver consists of germanium photodetectors

Survey of Photonic and Plasmonic Interconnect Technologies for Intra-Datacenter and High-Performance Computing Communications

Large scale data centers (DC) and high performance computing (HPC) systems require more and more computing power at higher energy efficiency. They are already consuming megawatts of power, and a linear extrapolation of trends reveals that they may eventually lead to unrealistic power consumption scenarios in order to satisfy future requirements (e.g., Exascale computing). Conventional complementary metal oxide semiconductor (CMOS)-based electronic interconnects are not expected to keep up with the envisioned future board-to-board and chip-to-chip (within multi-chip-modules) interconnect requirements because of bandwidth-density and power-consumption limitations. However, low-power and high-speed optics-based interconnects are emerging as alternatives for DC and HPC communications; they offer unique opportunities for continued energy-efficiency and bandwidth-density improvements, although cost is a challenge at the shortest length scales. Plasmonics-based interconnects on the other hand, due to their extremely small size, offer another interesting solution for further scaling operational speed and energy efficiency. At the device-level, CMOS compatibility is also an important issue, since ultimately photonics or plasmonics will have to be co-integrated with electronics. In this paper, we survey the available literature and compare the aforementioned interconnect technologies, with respect to their suitability for high-speed and energy-efficient on-chip and offchip communications. This paper refers to relatively short links with potential applications in the following interconnect distance hierarchy: local group of racks, board to board, module to module, chip to chip, and on chip connections. We compare different interconnect device modules, including low-energy output devices (such as lasers, modulators, and LEDs), photodetectors, passive devices (i.e., waveguides and couplers) and electrical circuitry (such as laserdiode drivers, modulator drivers, transimpedance, and limiting amplifiers). We show that photonic technologies have the potential to meet the requirements for selected HPC and DC applications in a shorter term. We also present that plasmonic interconnect modules could offer ultra-compact active areas, leading to high integration bandwidth densities, and low device capacitances allowing for ultra-high bandwidth operation that would satisfy the application requirements further into the future

Ultra-broadband surface-normal coherent optical receiver with nanometallic polarizers

A coherent receiver that can demodulate high-speed in-phase and quadrature signals of light is an essential component for optical communication, interconnects, imaging, and computing. Conventional waveguide-based coherent receivers, however, exhibit large footprints, difficulty in coupling a large number of spatial channels efficiently, and limited operating bandwidth imposed by the waveguide-based optical hybrid. Here, we present a surface-normal coherent receiver with nanometallic-grating-based polarizers integrated directly on top of photodetectors without the need for an optical hybrid circuit. Using a fabricated device with the active section occupying a 70-{\mu}m-square footprint, we demonstrate demodulation of high-speed (up to 64 Gbaud) coherent signals in various formats. Moreover, ultra-broadband operation from 1260 nm to 1630 nm is demonstrated, thanks to the wavelength-insensitive nanometallic polarizers. To our knowledge, this is the first demonstration of a surface-normal homodyne optical receiver, which can easily be scaled to a compact two-dimensional arrayed device to receive highly parallelized coherent signals.Comment: 23 pages, 4 figures (main manuscript) + 4 pages, 2 figures (supporting info

Surface-Normal Modulation of Fano Resonances in Metallic Photonic Crystals for Free-Space Optical Interconnects

This dissertation focuses on the development of ultra-compact optical devices for free-space modulation. We propose a surface-normal modulator using metallic photonic crystals for free-space optical interconnects. The active control of light intensity is achieved by engineering the Fano resonances in metallic photonic crystals. Both thermo-optic modulation and electro-optic modulation of the plasmonic bandgap are investigated, and bandgap tuning due to those effects is demonstrated. Additionally, the potential application of Fano resonances in metallic photonic crystals can be found in all-optical switching processing devices. Therefore, we show a hybrid plasmonic-organic nanostructure with extraordinary third harmonic generation emission at 1550 nm. Lastly, a simple method is proposed in this work to investigate the effect of finite grating size on Rayleigh anomaly-surface plasmon polariton (RA-SPP) resonances. The model could quickly and effectively predict the broadening of the transitional edges of RA-SPP resonances, which agrees well with experimental results quantitatively

Next Generation Silicon Photonic Transceiver: From Device Innovation to System Analysis

Silicon photonics is recognized as a disruptive technology that has the potential to reshape many application areas, for example, data center communication, telecommunications, high-performance computing, and sensing. The key capability that silicon photonics offers is to leverage CMOS-style design, fabrication, and test infrastructure to build compact, energy-efficient, and high-performance integrated photonic systems-on- chip at low cost. As the need to squeeze more data into a given bandwidth and a given footprint increases, silicon photonics becomes more and more promising. This work develops and demonstrates novel devices, methodologies, and architectures to resolve the challenges facing the next-generation silicon photonic transceivers. The first part of this thesis focuses on the topology optimization of passive silicon photonic devices. Specifically, a novel device optimization methodology - particle swarm optimization in conjunction with 3D finite-difference time-domain (FDTD), has been proposed and proven to be an effective way to design a wide range of passive silicon photonic devices. We demonstrate a polarization rotator and a 90◦ optical hybrid for polarization-diversity and phase-diversity communications - two important schemes to increase the communication capacity by increasing the spectral efficiency. The second part of this thesis focuses on the design and characterization of the next- generation silicon photonic transceivers. We demonstrate a polarization-insensitive WDM receiver with an aggregate data rate of 160 Gb/s. This receiver adopts a novel architecture which effectively reduces the polarization-dependent loss. In addition, we demonstrate a III-V/silicon hybrid external cavity laser with a tuning range larger than 60 nm in the C-band on a silicon-on-insulator platform. A III-V semiconductor gain chip is hybridized into the silicon chip by edge-coupling to the silicon chip. The demonstrated packaging method requires only passive alignment and is thus suitable for high-volume production. We also demonstrate all silicon-photonics-based transmission of 34 Gbaud (272 Gb/s) dual-polarization 16-QAM using our integrated laser and silicon photonic coherent transceiver. The results show no additional penalty compared to commercially available narrow linewidth tunable lasers. The last part of this thesis focuses on the chip-scale optical interconnect and presents two different types of reconfigurable memory interconnects for multi-core many-memory computing systems. These reconfigurable interconnects can effectively alleviate the memory access issues, such as non-uniform memory access, and Network-on-Chip (NoC) hot-spots that plague the many-memory computing systems by dynamically directing the available memory bandwidth to the required memory interface

Strategies for optimizing plasmonic grating couplers with topology-based inverse design

Numerical simulations have become a cornerstone technology in the development of nanophotonic devices. Specifically, 3D finite difference time domain (FDTD) simulations are a widely used due to their flexibility and powerful design capabilities. More recently, FDTD simulations in conjunction with a design methodology called inverse design has become a popular way to optimize device topology, reducing a device's footprint and increasing performance. We implement a commercial inverse design tool to generate complex grating couplers and explore a variety of grating coupler design methodologies. We compare the conventionally designed grating couplers to those generated by the inverse design tool. Finally, we discuss the limitations of the inverse design tool and how different design strategies for grating couplers affect inverse design performance, both in terms of computational cost and performance of the resulting device

Graphene Modulators for Silicon Photonic Optical Links

The backbone of today’s society is the transfer of information. Next-generation data network infrastructures need to support Tb/s data rates. Existing optical fibre communication networks cannot support Tb/s data transmission without consuming an unsustainable amount of power. Optical transceivers send and receive information encoded in light, relying on electro-optic modulators to convert the electrical data signal into the optical domain, and photodetectors to convert the optical signal back into the electrical domain. Power consumption can be reduced by using efficient and compact modulators and photodetectors to integrate the optics closer to the electronics and thus minimise the losses of electrical interconnect at high frequencies. Si photonics technology offers a cost-effective solution for fabricating integrated photonic circuits by combining electronic and photonic components in the same circuit by using existing CMOS technology. This thesis focuses on the development of a scalable graphene-based platform for integrated photonics, and specifically on the electrooptic modulator. I have focused on a double single-layer graphene modulator design in three different configurations that can be used for different types of optical links. This includes a graphene-based electro-absorption modulator, ring resonator modulator, and Mach-Zehnder modulator. The double-layer structure enables the absorption and phase of an optical carrier signal to be electrostatically controlled without the need for doped waveguides. This is the most efficient graphene-based phase modulator to-date with an extracted VπL ∼ 0.12 V·cm, which is ∼ 2 times better than the lowest reported graphene phase modulator. As well as showing very efficient phase modulation, the graphene phase modulator is capable of being operated in the transparency regime where graphene becomes transparent to absorption via interband transitions. Operating in the transparency regime means that the graphene phase modulator is capable of pure phase modulation which is a desirable property for complex modulation formats. Benefiting from efficient phase modulation, the graphene ring resonator modulator has demonstrated an FOM(EA) ∼ 4.48, ∼ 2 times better than the highest currently reported for graphene-based modulators. These results represent a step towards the development of a future graphene-based platform for efficient and compact modulators and photodetectors needed for next-generation optical links