High Data-Rate, Battery-Free, Active Millimeter-Wave Identification Technologies for Future Integrated Sensing, Tracking, and Communication Systems-On-Chip

RÉSUMÉ Pour de nombreuses applications allant de la sécurité, le contrôle d'accès, la surveillance et la gestion de la chaîne d'approvisionnement aux applications biomédicales et d'imagerie parmi tant d'autres, l'identification par radiofréquence (RFID) a énormément influencé notre quotidien. Jusqu'à présent, cette technologie émergente a été la plupart du temps conçue et développé dans les basses fréquences (en dessous de 3 GHz). D’une part, pour des applications où de courte distances (quelques centimètres) et à faible taux de communications de données sont suffisantes (même préférables dans certains cas), la technologie RFID à couplage inductif qui fonctionne à basse fréquences (LF) ou à haute fréquences (HF) fonctionne très bien et elle est largement utilisée dans de nombreuses applications commerciales. D'autre part, afin d’augmenter la distance de communication (quelques mètres), le débit de données de communication, et ainsi minimiser la taille du tag, la technologie RFID fonctionnant dans la bande d’ultra-haute fréquence (UHF) et aux fréquences micro-ondes (par exemple, 2.4 GHz) a récemment attiré beaucoup d'attention dans le milieu de la recherche et le développement. Cependant, dans ces bandes de fréquences, une bande passante disponible restreinte avec la taille du tag assez large (principalement dominée par la taille d'antenne et de la batterie dans le cas d'un tag actif) sont les principaux facteurs qui ont toujours limité l'évolution de la technologie RFID actuelle. En effet, propulser la technologie RFID dans la bande de fréquences à ondes millimétriques briserait les barrières actuelles de la technologie RFID. La technologie d’identification aux fréquences à ondes millimétriques (MMID) offre plus de bande passante, et permet également la miniaturisation de la taille du tag, car à ces bandes de fréquences, la longueur d’onde est de l’ordre de quelques millimètres, une taille comparable à la taille d’un circuit intégré. L'antenne peut donc être soit intégré sur la même puce (antenne sur puce) ou soit encapsulé dans le même boitier que le circuit intégré. En dotant le tag la capacité de récolter sans fil son énergie à partir d'un signal aux fréquences à ondes millimétriques provenant du lecteur, lui fournissant ainsi l'autonomie énergétique (ainsi éliminant la nécessité d'une batterie et en même temps permettant la miniaturisation du tag), il devient alors possible d'intégrer entièrement tout le tag MMID sur une seule puce y compris les antennes, ce qui aboutira à la mise au point d’une nouvelle technologie miniature (μRFID) fonctionnant à la bande de fréquences à ondes millimétriques.----------ABSTRACT For countless applications ranging from security, access control, monitoring, and supply chain management to biomedical and imaging applications among many others, radio frequency identification (RFID) technology has tremendously impacted our daily life. So far, this ever-needed and emerging technology has been mostly designed and developed at low RF frequencies (below 3-GHz). For many practical applications where short-range (few centimeters) and low data-rate communications are sufficient and in some cases even preferable, inductively coupled RFID systems that operate over either low-frequency (LF) or high-frequency (HF) bands have performed quite well and have been widely used for practical and commercial applications. On the other hand, in the quest for a longer communication range (few meters), relatively high data-rate and smaller antenna size RFID systems operating over ultra-high frequency (UHF) and microwave frequency bands (e.g., 2.4-GHz) have recently attracted much attention in the research and development community. However, over these RF bands, a restricted available bandwidth together with an undesired tag size (mainly dominated by its off-chip antenna size and battery in the case of active tag) are the main factors that have been limiting the evolution of today’s RFID technology. Indeed, propelling RFID technology into millimeter-wave frequencies opens up new applications that cannot be made possible today.Millimeter-wave identification (MMID) technology is set out to exploit significantly larger bandwidth and smaller antenna size. Over these frequency bands, an effective wavelength is in the order of a few millimeters, hence close to a typical semiconductor (CMOS) die size. The antenna, therefore, may either be integrated on the same chip (antenna-on-chip – AoC) or embedded in the related package (antenna-in-package – AiP). In addition, by equipping the tag with the capability to wirelessly harvest its energy from an incoming millimeter-wave signal, thereby providing energy autonomy without the need of a battery and at the same time allowing miniaturization, it becomes possible to integrate the entire MMID tag circuitry on a single chip. Furthermore, the timely MMID concept is fully compatible with upcoming and future applications of millimeter-wave technology in wireless communications which are being discussed and developed worldwide in research and development communities, such as the internet of things (IoT), 5G, autonomous mobility, μSmart sensors, automotive RADAR technologies, etc

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Silicon Integrated Arrays: From Microwave to IR

Integrated chips have enabled realization and mass production of complex systems in a small form factor. Through process miniaturization many novel applications in silicon photonics and electronic systems have been enabled. In this thesis I have provided several examples of innovations that are only enabled by integration. I have also demonstrated how electronics and photonics circuits can complement each other to achieve a system with superior performance.</p

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Remotely interrogated MEMS pressure sensor

This thesis considers the design and implementation of passive wireless microwave readable pressure sensors on a single chip. Two novel-all passive devices are considered for wireless pressure operation. The first device consists of a tuned circuit operating at 10 GHz fabricated on SiO2 membrane, supported on a silicon wafer. A pressure difference across the membrane causes it to deflect so that a passive resonant circuit detunes. The circuit is remotely interrogated to read off the sensor data. The chip area is 20 mm2 and the membrane area is 2mm2 with thickness of 4 µm. Two on chip passive resonant circuits were investigated: a meandered dipole and a zigzag antenna. Both have a physical length of 4.25 mm. the sensors show a shift in their resonant frequency in response to changing pressure of 10.28-10.27 GHz for the meandered dipole, and 9.61-9.58 GHz for the zigzag antenna. The sensitivities of the meandered dipole and zigzag sensors are 12.5 kHz and 16 kHz mbar, respectively. The second device is a pressure sensor on CMOS chip. The sensing element is capacitor array covering an area of 2 mm2 on a membrane. This sensor is coupled with a dipole antenna operating at 8.77 GHz. The post processing of the CMOS chip is carried out only in three steps, and the sensor on its own shows a sensitivity of 0.47fF/mbar and wireless sensitivity of 27 kHz/mbar. The MIM capacitors on membrane can be used to detune the resonant frequency of an antenna

Impedance matching and DC-DC converter designs for tunable radio frequency based mobile telecommunication systems

Tunability and adaptability for radio frequency (RF) front-ends are highly desirable because they not only enhance functionality and performance but also reduce the circuit size and cost. This thesis presents a number of novel design strategies in DC-DC converters, impedance networks and adaptive algorithms for tunable and adaptable RF based mobile telecommunication systems. Specifically, the studies are divided into three major directions: (a) high voltage switch controller based DC-DC converters for RF switch actuation; (b) impedance network designs for impedance transformation of RF switches; and (c) adaptive algorithms for determining the required impedance states at the RF switches. In the first stage, two-phase step-up switched-capacitor (SC) DC-DC converters are explored. The SC converter has a simple control method and a reduced physical volume. The research investigations started with the linear and the non-linear voltage gain topologies. The non-linear voltage gain topology provides a higher voltage gain in a smaller number of stages compared to the linear voltage gain topology. Amongst the non-linear voltage gain topologies, a Fibonacci SC converter has been identified as having lower losses and a higher conversion ratio compared to other topologies. However, the implementation of a high voltage (HV) gain Fibonacci SC converter is complex due to the requirement of widely different gate voltages for the transistors in the Fibonacci converter. Gate driving strategies have been proposed that only require a few auxiliary transistors in order to provide the required boosted voltages for switching the transistors on and off. This technique reduces the design complexity and increases the reliability of the HV Fibonacci SC converter. For the linear voltage gain topology, a high performance complementary-metaloxide- semiconductor (CMOS) based SC DC-DC converter has been proposed in this work. The HV SC DC-DC converter has been designed in low voltage (LV) transistors technology in order to achieve higher voltage gain. Adaptive biasing circuits have been proposed to eliminate the leakage current, hence avoiding latch-up which normally occurs with low voltage transistors when they are used in a high voltage design. Thus, the SC DC-DC converter achieves more than 25% higher boosted voltage compared to converters that use HV transistors. The proposed design provides a 40% power reduction through the charge recycling circuit that reduces the effect of non-ideality in integrated HV capacitors. Moreover, the SC DC-DC converter achieves a 45% smaller area than the conventional converter through optimising the design parameters. In the second stage, the impedance network designs for transforming the impedance of RF switches to the maximum achievable impedance tuning region are investigated. The maximum achievable tuning region is bounded by the fundamental properties of the selected impedance network topology and by the tunable values of the RF switches that are variable over a limited range. A novel design technique has been proposed in order to achieve the maximum impedance tuning region, through identifying the optimum electrical distance between the RF switches at the impedance network. By varying the electrical distance between the RF switches, high impedance tuning regions are achieved across multi frequency standards. This technique reduces the cost and the insertion loss of an impedance network as the required number of RF switches is reduced. The prototype demonstrates high impedance coverages at LTE (700MHz), GSM (900MHz) and GPS (1575MHz). Integration of a tunable impedance network with an antenna for frequency-agility at the RF front-end has also been discussed in this work. The integrated system enlarges the bandwidth of a patch antenna by four times the original bandwidth and also improves the antenna return loss. The prototype achieves frequency-agility from 700MHz to 3GHz. This work demonstrates that a single transceiver with multi frequency standards can be realised by using a tunable impedance network. In the final stage, improvement to an adaptive algorithm for determining the impedance states at the RF switches has been proposed. The work has resulted in one more novel design techniques which reduce the search time in the algorithm, thus minimising the risk of data loss during the impedance tuning process. The approach reduces the search time by more than an order of magnitude by exploiting the relationships among the mass spring’s coefficient values derived from the impedance network parameters, thereby significantly reducing the convergence time of the algorithm. The algorithm with the proposed technique converges in less than half of the computational time compared to the conventional approach, hence significantly improving the search time of the algorithm. The design strategies proposed in this work contribute towards the realisation of tunable and adaptable RF based mobile telecommunication systems

Learning-Based Hardware Design for Data Acquisition Systems

This multidisciplinary research work aims to investigate the optimized information extraction from signals or data volumes and to develop tailored hardware implementations that trade-off the complexity of data acquisition with that of data processing, conceptually allowing radically new device designs. The mathematical results in classical Compressive Sampling (CS) support the paradigm of Analog-to-Information Conversion (AIC) as a replacement for conventional ADC technologies. The AICs simultaneously perform data acquisition and compression, seeking to directly sample signals for achieving specific tasks as opposed to acquiring a full signal only at the Nyquist rate to throw most of it away via compression. Our contention is that in order for CS to live up its name, both theory and practice must leverage concepts from learning. This work demonstrates our contention in hardware prototypes, with key trade-offs, for two different fields of application as edge and big-data computing. In the framework of edge-data computing, such as wearable and implantable ecosystems, the power budget is defined by the battery capacity, which generally limits the device performance and usability. This is more evident in very challenging field, such as medical monitoring, where high performance requirements are necessary for the device to process the information with high accuracy. Furthermore, in applications like implantable medical monitoring, the system performances have to merge the small area as well as the low-power requirements, in order to facilitate the implant bio-compatibility, avoiding the rejection from the human body. Based on our new mathematical foundations, we built different prototypes to get a neural signal acquisition chip that not only rigorously trades off its area, energy consumption, and the quality of its signal output, but also significantly outperforms the state-of-the-art in all aspects. In the framework of big-data and high-performance computation, such as in high-end servers application, the RF circuits meant to transmit data from chip-to-chip or chip-to-memory are defined by low power requirements, since the heat generated by the integrated circuits is partially distributed by the chip package. Hence, the overall system power budget is defined by its affordable cooling capacity. For this reason, application specific architectures and innovative techniques are used for low-power implementation. In this work, we have developed a single-ended multi-lane receiver for high speed I/O link in servers application. The receiver operates at 7 Gbps by learning inter-symbol interference and electromagnetic coupling noise in chip-to-chip communication systems. A learning-based approach allows a versatile receiver circuit which not only copes with large channel attenuation but also implements novel crosstalk reduction techniques, to allow single-ended multiple lines transmission, without sacrificing its overall bandwidth for a given area within the interconnect's data-path