Methodology to Improve Switching Speed of SiC MOSFETs in Hard Switching Applications

To meet the higher efficiency and power density requirement for power converters, the switching speed of power devices is preferred to increase. Thanks to silicon carbide (SiC) power MOSFETs, their intrinsic superior switching characteristics compared with silicon IGBTs makes it possible to run converters at faster switching speed in hard switching applications. Nevertheless, the switching speed is not only dependent on the device’s characteristics, but also strongly related to the circuit like gate drive and parasitics. To fully utilize the potential of SiC MOSFETs, the impact factors limiting the switching speed are required to be understood. Specific solutions and methods need to be developed to mitigate the influence from these impact factors.The characterization of the switching speed for SiC MOSFETs with different current ratings is conducted with double pulse test (DPT) first. Based on the result, the impact factors of switching speed are evaluated in detail.According to the evaluation, the switching speed of SiC discrete devices with low current rating is mainly limited by the gate drive capability. A current source gate drive as well as a charge pump gate drive are proposed, which can provide higher current during the switching transient regardless of the low transconductance and large internal gate resistance of SiC discrete devices.For SiC power modules with high current rating, the switching speed is mainly determined by the device drain-source overvoltage resulting from circuit parasitics. An analytical model for the multiple switching loops related overvoltage in 3L-ANPC converters is established. A simple modulation is developed to mitigate the effect of the non-linear device output capacitance, which helps reduce the overvoltage and enables higher switching speed operation of SiC power modules.Furthermore, the layout design methodology for three-level converters concerning the multiple commutation loops is introduced. The development of a laminated busbar for a 500 kVA 3L-ANPC converter with SiC power modules is presented in detail.Finally, a SiC based 1 MW inverter is built and tested to operate at cryogenic temperature. The proposed control and busbar above are utilized to increase the switching speed of the SiC power module

Investigation of FACTS devices to improve power quality in distribution networks

Flexible AC transmission system (FACTS) technologies are power electronic solutions that improve power transmission through enhanced power transfer volume and stability, and resolve quality and reliability issues in distribution networks carrying sensitive equipment and non-linear loads. The use of FACTS in distribution systems is still in its infancy. Voltages and power ratings in distribution networks are at a level where realistic FACTS devices can be deployed. Efficient power converters and therefore loss minimisation are crucial prerequisites for deployment of FACTS devices. This thesis investigates high power semiconductor device losses in detail. Analytical closed form equations are developed for conduction loss in power devices as a function of device ratings and operating conditions. These formulae have been shown to predict losses very accurately, in line with manufacturer data. The developed formulae enable circuit designers to quickly estimate circuit losses and determine the sensitivity of those losses to device voltage and current ratings, and thus select the optimal semiconductor device for a specific application. It is shown that in the case of majority carrier devices (such as power MOSFETs), the conduction power loss (at rated current) increases linearly in relation to the varying rated current (at constant blocking voltage), but is a square root of the variable blocking voltage when rated current is fixed. For minority carrier devices (such as a pin diode or IGBT), a similar relationship is observed for varying current, however where the blocking voltage is altered, power losses are derived as a square root with an offset (from the origin). Finally, this thesis conducts a power loss-oriented evaluation of cascade type multilevel converters suited to reactive power compensation in 11kV and 33kV systems. The cascade cell converter is constructed from a series arrangement of cell modules. Two prospective structures of cascade type converters were compared as a case study: the traditional type which uses equal-sized cells in its chain, and a second with a ternary relationship between its dc-link voltages. Modelling (at 81 and 27 levels) was carried out under steady state conditions, with simplified models based on the switching function and using standard circuit simulators. A detailed survey of non punch through (NPT) and punch through (PT) IGBTs was completed for the purpose of designing the two cascaded converters. Results show that conduction losses are dominant in both types of converters in NPT and PT IGBTs for 11kV and 33kV systems. The equal-sized converter is only likely to be useful in one case (27-levels in the 33kV system). The ternary-sequence converter produces lower losses in all other cases, and this is especially noticeable for the 81-level converter operating in an 11kV network

Design and Switching Performance Evaluation of a 10 kV SiC MOSFET Based Phase Leg for Medium Voltage Applications

10 kV SiC MOSFETs are promising to substantially boost the performance of future medium voltage (MV) converters, ranging from MV motor drives to fast charging stations for electric vehicles (EVs). Numerous factors influence the switching performance of 10 kV SiC MOSFETs with much faster switching speed than their Si counterparts. Thorough evaluation of their switching performance is necessary before applying them in MV converters. Particularly, the impact of parasitic capacitors in the MV converter and the freewheeling diode is investigated to understand the switching performance more comprehensively and guide the converter design based on 10 kV SiC MOSFETs.A 6.5 kV half bridge phase leg based on discrete 10 kV/20 A SiC MOSFETs is designed and fully validated to operate continuously at rated voltage with dv/dt up to 80 V/ns. Based on the phase leg, the impact of parasitic capacitors brought by the load inductor and the heatsink on the switching transients and performance of 10 kV SiC MOSFETs is investigated. Larger parasitic capacitors result in more oscillations, longer switching transients, as well as higher switching energy loss especially at low load current. As for the freewheeling diode, the body diode of 10 kV SiC MOSFETs is suitable to serve as the freewheeling diode, with negligible reverse recovery charge at various temperatures. The switching performance with and without the anti-parallel SiC junction barrier Schottky (JBS) diode is compared quantitatively. It is not recommended to add an anti-parallel diode for the 10 kV SiC MOSFET in the converter because it increases the switching loss

Characterization Methodology, Modeling, and Converter Design for 600 V Enhancement-Mode GaN FETs

Gallium Nitride (GaN) power devices are an emerging technology that have only become available commercially in the past few years. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This dissertation reviews the unique characteristics, commercial status, and design challenges that surround GaN FETs, in order to provide sufficient background to potential GaN-based converter designers.Methodology for experimentally characterizing a GaN FET was also presented, including static characterization with a curve tracer and impedance analyzer, as well as dynamic characterization in a double pulse test setup. This methodology was supplemented by additional tests to determine losses caused by Miller-induced cross talk, and the tradeoff between these losses and overlap losses was studied for one example device.Based on analysis of characterization results, a simplified model was developed to describe the overall switching behavior and some unique features of the device. The impact of the Miller effect during the turn-on transient was studied, as well as the dynamic performance of GaN at elevated temperature.Furthermore, solutions were proposed for several key design challenges in GaN-based converters. First, a driver-integrated overcurrent and short-circuit protection scheme was developed, based on the relationship between gate voltage and drain current in GaN gate injection transistors. Second, the limitations on maximum utilization of current and voltage in a GaN FET were studied, particularly the voltage overshoots following turn-on and turn-off switching transients, and the effective cooling of GaN FETs in higher power operation. A thermal design was developed for heat extraction from bottom-cooled surface-mount devices. These solutions were verified in a GaN-based full-bridge single-phase inverter

Optimisation of High Reliability Integrated Motor Drives

The development of integrated motor drives (IMDs) with high volumetric power density and reliability are crucial for the continued development and adoption of electric vehicles (EV). The development of the wide bandgap (WBG) devices, especially Silicon Carbide (SiC) MOSFETs, enables new possibilities for traction drive systems. However, to maximise the benefits of SiC, the IMD design process, including passive component selection, control and thermal management should be optimised. This thesis goes through the initial major design steps in SiC power system design, from SiC device analysis and modelling to circuit design and electrothermal simulation of an IMD system. A novel approach to discrete SiC MOSFET selection, using a method of calculating performance based on experimental data, is described. Dynamic behaviour of a family of 1200 V MOSFETs is studied at temperatures up to 175 °C using a double pulse test to show the combined effect of the differences in internal design between MOSFETs with different current ratings. It is observed that the 30 mΩ MOSFET had a 24 % higher switching loss than a 140 mΩ at a 30 A load current. The study then goes on to compare the effect of switching frequency, paralleling of MOSFETs and the device type used to demonstrate the inverter design with the lowest power losses, which will equate to low temperatures and high lifetime. The novel methodology can find the optimal choice of MOSFET from the family, and number required through paralleling, for a circuit when given the load current, temperature and switching. Understanding the device interdependencies in a single family is utilised to also predict the relative performance between SiC MOSFETs from different manufacturers. An axial-flux permanent magnet synchronous motor (PMSM) driven by a three-phase SiC inverter is simulated in PLECS using experimentally validated MOSFET models chosen by the device selection methodology. Electrothermal analysis shows the influence of switching frequency, temperature, MOSFETs paralleling and DC-link capacitance on voltage ripple, total harmonic distortion, efficiency and MOSFET loss and temperature profiles. With a 60 % decrease in THD and 50 % increase in maximum MOSFET junction temperature when switching frequency is increased from 10 to 100 kHz. The high-temperature stress on the semiconductors due to close proximity with the ma- chine stator means reliability is an important consideration that is yet to be fully investigated in IMD optimisations. This study uses a lifetime model specific to the transistor package TO-247 in reliability optimisation for IMD for the first time. It requires detailed MOSFET simulation outputs to provide a highly accurate lifetime for discrete SiC MOSFETs. Both single and multi-objective optimisations of the volume and lifetime of the three- phase inverter are presented. The single objective optimisation demonstrates the minimum volume and the corresponding switching frequency and lifetime when between three and six MOSFETs are paralleled at a temperature range between 50 and 150 °C. Design constraints were set limiting the feasible switching frequency range to between 13 kHz because of THD and 118 kHz because of efficiency limits, corresponding to required DC-link capacitors of 520 and 55 μF respectively. Increases in temperature were found to further limit the maximum switching frequency and therefore increase the minimum volume of the inverter. A Pareto front identifies a range of possible solutions for the volume and lifetime of an inverter with six paralleled MOSFETs through the multi-objective objective procedure. Further analysis of these possible solutions identified a single optimal solution for the system, using a DC-link capacitance of 190 μF at 45 kHz, giving a combined volume of the capacitor and MOSFETs of 440 cm3 and a lifetime of 12,000 hours. Finally, the electrothermal analysis of a dual inverter driving a symmetric six-phase PMSM is presented with the benefits of modular multi-phase systems in IMDs summarised. Effect on performance of lower per-phase current, interleaving strategies and fault tolerance are analysed and compared to equivalent three-phase systems, for 60 kW and 120 kW operation. A novel method for lifetime prediction of systems with paralleled MOSFETs or fault tolerance capabilities considering incremental damage is developed based on TO-247 lifetime calculations from PLECS simulation, and component-level reliability profiles using Monte Carlo analysis. The dual inverter is used to model the system and implements control schemes for both single-phase and single inverter failure while maintaining the 4000 rpm and 140 Nm speed and torque requirements. A twofold increase in B10 lifetime of is observed when the effect of paralleled SiC MOSFETs prevents immediate system failure in a three-phase inverter. A computational fluid dynamics (CFD) and 3D finite element thermal model are designed to study the inverter behaviour based on the thermal analysis of its shared cooling plate with a 300 mm diameter axial flux PMSM. Concentric layout designs minimise the variation of junction temperatures to 5 °C and the effect of the flow rate and temperature of the coolant in the PMSM cold plate is presented between 5 and 30 l/min. The multi-objective optimisation procedure used to compare the dual inverter demonstrated it outperformed the three-phase inverter with 15 % smaller required DC-link capacitance, higher efficiency and increased lifetime in part due to its fault-tolerant nature. The optimal dual inverter considering the design constraints consists of four 40 μF KEMET film capacitors operating with a switching frequency of 46 kHz giving an inverter volume of 300 cm3 and a lifetime of 16.3 years, assuming 1000 hours of operation annually

Driving and Protection of High Density High Temperature Power Module for Electric Vehicle Application

There has been an increasing trend for the commercialization of electric vehicles (EVs) to reduce greenhouse gas emissions and dependence on petroleum. However, a key technical barrier to their wide application is the development of high power density electric drive systems due to limited space within EVs. High temperature environment inherent in EVs further introduces a new level of complexity. Under high power density and high temperature operation, system reliability and safety also become important. This dissertation deals with the development of advanced driving and protection technologies for high temperature high density power module capable of operating under the harsh environment of electric vehicles, while ensuring system reliability and safety under short circuit conditions. Several related research topics will be discussed in this dissertation. First, an active gate driver (AGD) for IGBT modules is proposed to improve their overall switching performance. The proposed one has the capability of reducing the switching loss, delay time, and Miller plateau duration during turn-on and turn-off transient without sacrificing current and voltage stress. Second, a board-level integrated silicon carbide (SiC) MOSFET power module is developed for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI) based gate driver board is designed and fabricated through chip-on-board (COB) technique. Also, a 1200 V / 100 A SiC MOSFET phase-leg power module is developed utilizing high temperature packaging technologies. Third, a comprehensive short circuit ruggedness evaluation and numerical investigation of up-to-date commercial silicon carbide (SiC) MOSFETs is presented. The short circuit capability of three types of commercial 1200 V SiC MOSFETs is tested under various conditions. The experimental short circuit behaviors are compared and analyzed through numerical thermal dynamic simulation. Finally, according to the short circuit ruggedness evaluation results, three short circuit protection methods are proposed to improve the reliability and overall cost of the SiC MOSFET based converter. A comparison is made in terms of fault response time, temperature dependent characteristics, and applications to help designers select a proper protection method

Online Switching Time Monitoring of SiC Devices Using Intelligent Gate Driver for Converter Performance Improvement

Most intelligent gate drivers designed for new state of the art WBG devices typically only focus on protection and driving capabilities of the devices. This paper introduces an intelligent gate driver that incorporates online switching time monitoring of silicon carbide (SiC) devices. For this specific case study, three timing conditions (turn-off delay time, turn-off time, and voltage commutation time) of a SiC phase-leg are online monitored. This online monitoring system is achieved through transient detection circuits and a micro-controller. These timing conditions are then utilized to develop converter-level benefits for a voltage-source inverter application using SiC devices. Junction temperature monitoring is realized through turn-off delay time monitoring. Dead-time optimization is achieved with turn-off time monitoring. Dead-time compensation is obtained with turn-off time and voltage commutation time monitoring. The case study converter assembled for testing purposes is a half-bridge inverter using two SiC devices in a phase-leg configuration. All timing conditions are correctly monitored within reasonable difference of the actual condition time. The half-bridge inverter can operate at 600 V DC input and successfully obtain a junction temperature measurement through monitored turn-off delay time and the calibration curve. In addition, dead-time control is realized to reduce device power loss and improve AC output power quality. Furthermore, the proposed online time monitoring system is board-level integrated with the gate driver and suitable for the chip level integration, enabling this practical approach to be cost-effective for end users

Switching Performance Evaluation, Design, and Test of a Robust 10 kV SiC MOSFET Based Phase Leg for Modular Medium Voltage Converters

10 kV SiC MOSFETs are one of the most promising power semiconductor devices for next-generation high-performance modular medium voltage (MV) converters. With extraordinary device characteristics, 10 kV SiC MOSFETs also bring a variety of challenges in the design and test of MV converters. To tackle these inherent challenges, this dissertation focuses on a robust half bridge (HB) phase leg based on 10 kV SiC MOSFETs for modular MV converters. A baseline design and test of the phase leg is established first as the foundation of the research in this dissertation. Thorough evaluation of 10 kV SiC MOSFETs’ switching performance in a phase leg is necessary before applying them in MV converters. The impact of parasitic capacitors and the freewheeling diode is investigated to understand the switching performance more extensively and guide the converter design. One non-negligible challenge is the flashover fault resulting from the premature insulation breakdown, a short circuit fault with extremely fast transients. A device model is established to analyze the behavior of 10 kV SiC MOSFETs when the fault occurs in a phase leg thoroughly. Subsequently, the gate driver and protection design considerations are summarized to achieve lower short circuit current and overvoltage and ensure the survival of the MOSFET that in ON state when the fault happens. Furthermore, it is challenging to design the overcurrent/short circuit protection with fast response and strong noise immunity under fast switching transients for 10 kV SiC MOSFETs. The noise immunity of the desaturation (desat) protection is studied quantitatively to provide design guidelines for noise immunity enhancement. Then, the protection scheme based on desat protection is developed and validated withimmunity, the strong noise immunity of the developed protection is also successfully validated. In addition, a simple test scheme is proposed and validated experimentally, in order to qualify the HB phase leg based on the 10 kV SiC MOSFET comprehensively for the modular MV converter applications. The test scheme includes the ac-dc continuous test with two phase legs in series to create the testing condition similar to what is generated in a modular MV converter, especially the high dv/dt. The test scheme can fully test the capability of the phase leg to withstand high dv/dt and its resulting noise

Review and Characterization of Gallium Nitride Power Devices

Gallium Nitride (GaN) power devices are an emerging technology that have only recently become available commercially. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This thesis reviews the characteristics and commercial status of both vertical and lateral GaN power devices from the user perspective, providing the background necessary to understand the significance of these recent developments. Additionally, the challenges encountered in GaN-based converter design are considered, such as the consequences of faster switching on gate driver design and board layout. Other issues include the unique reverse conduction behavior, dynamic on-resistance, breakdown mechanisms, thermal design, device availability, and reliability qualification. Static and dynamic characterization was then performed across the full current, voltage, and temperature range of this device to enable effective GaN-based converter design. Static testing was performed with a curve tracer and precision impedance analyzer. A double pulse test setup was constructed and used to measure switching loss and time at the fastest achievable switching speed, and the subsequent overvoltages due to the fast switching were characterized. The results were also analyzed to characterize the effects of cross-talk in the active and synchronous devices of a phase-leg topology with enhancement-mode GaN HFETs. Based on these results and analysis, an accurate loss model was developed for the device under test. Based on analysis of these characterization results, a simplified model was developed to describe the overall switching behavior and some unique features of the device. The consequences of the Miller effect during the turn-on transient were studied to show that no Miller plateau occurs, but rather a decreased gate voltage slope, followed by a sharp drop. The significance of this distinction is derived and explained. GaN performance at elevated temperature was also studied, because turn-on time increases significantly with temperature, and turn-on losses increase as a result. Based on this relationship, a temperature-dependent turn-on model and a linear scaling factor was proposed for estimating turn-on loss in e-mode GaN HFETs