Clustering in ICT: From Route 128 to Silicon Valley, from DEC to Google, from Hardware to Content

One of the pioneers in academic entrepreneurship and high-tech clustering is MIT and the Route 128/Boston region. Silicon Valley centered around Stanford University was originally a fast follower and only later emerged as a scientific and industrial hotspot. Several technology and innovation waves, have shaped Silicon Valley over all the years. The initial regional success of Silicon Valley started with electro-technical instruments and defense applications in the 1940s and 1950s (represented by companies as Litton Engineering and Hewlett & Packard). In the 1960s and 1970s, the region became a national and international leader in the design and production of integrated circuit and computer chips, and as such became identified as Silicon Valley (e.g. Fairchild Semiconductor, and Intel). In the 1970s and 1980s, Silicon Valley capitalised further on the development, manufacturing and sales of the personal computer and workstations (e.g. Apple, Silicon Graphics and SUN), followed by the proliferation of telecommunications and Internet technologies in the 1990s (e.g. Cisco, 3Com) and Internet-based applications and info-mediation services (e.g. Yahoo, Google) in the late 1990s and early 2000s. When the external and/or internal conditions of its key industries change, Silicon Valley seemed to have an innate capability to restructure itself by a rapid and frequent reshuffling of people, competencies, resources and firms. To characterise the demise of one firm leading, directly or indirectly, to the formation of another and the reconfiguration of business models and product offerings by the larger companies in emerging industries, Bahrami & Evans (2000) introduced the term `flexible recycling.’ This dynamic process of learning by doing, failing and recombining (i.e. allowing new firms to rise from the ashes of failed enterprises) is one of the key factors underlying the dominance of Silicon Valley in the new economy.ICT;Clusters;Networks;Academic entrepreneurship;MIT;Silicon Valley;Stanford University;Flexible recycling;Route 128

Memory and information processing in neuromorphic systems

A striking difference between brain-inspired neuromorphic processors and current von Neumann processors architectures is the way in which memory and processing is organized. As Information and Communication Technologies continue to address the need for increased computational power through the increase of cores within a digital processor, neuromorphic engineers and scientists can complement this need by building processor architectures where memory is distributed with the processing. In this paper we present a survey of brain-inspired processor architectures that support models of cortical networks and deep neural networks. These architectures range from serial clocked implementations of multi-neuron systems to massively parallel asynchronous ones and from purely digital systems to mixed analog/digital systems which implement more biological-like models of neurons and synapses together with a suite of adaptation and learning mechanisms analogous to the ones found in biological nervous systems. We describe the advantages of the different approaches being pursued and present the challenges that need to be addressed for building artificial neural processing systems that can display the richness of behaviors seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed neuromorphic computing platforms and system

Infrastructure for Detector Research and Development towards the International Linear Collider

The EUDET-project was launched to create an infrastructure for developing and testing new and advanced detector technologies to be used at a future linear collider. The aim was to make possible experimentation and analysis of data for institutes, which otherwise could not be realized due to lack of resources. The infrastructure comprised an analysis and software network, and instrumentation infrastructures for tracking detectors as well as for calorimetry.Comment: 54 pages, 48 picture

Belle II Technical Design Report

The Belle detector at the KEKB electron-positron collider has collected almost 1 billion Y(4S) events in its decade of operation. Super-KEKB, an upgrade of KEKB is under construction, to increase the luminosity by two orders of magnitude during a three-year shutdown, with an ultimate goal of 8E35 /cm^2 /s luminosity. To exploit the increased luminosity, an upgrade of the Belle detector has been proposed. A new international collaboration Belle-II, is being formed. The Technical Design Report presents physics motivation, basic methods of the accelerator upgrade, as well as key improvements of the detector.Comment: Edited by: Z. Dole\v{z}al and S. Un

A survey of system level power management schemes in the dark-silicon era for many-core architectures

Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with many-core integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints