Architectures for RF Frequency synthesizers

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.\ud Written for:\ud Electrical and electronic engineer

Linear phase demodulator including a phase locked loop with auxiliary feedback loop

A phase modulated wave that may have no carrier power is demodulated by a phase locked loop including a phase detector for deriving an A.C. data output signal having a magnitude and a phase indicative of the phase of the modulated wave. A feedback loop responsive to the data output signal restores power to the carrier frequency component to the loop. In one embodiment, the feedback loop includes a phase modulator responsive to the phase modulated wave and the data output signal. In a second embodiment, carrier frequency power is restored by differentiating the data output signal and supplying the differentiated signal to an input of a voltage controlled oscillator included in the phase locked loop

Hardware simulation of Ku-band spacecraft receiver and bit synchronizer, volume 1

A hardware simulation which emulates an automatically acquiring transmit receive spread spectrum communication and tracking system and developed for use in future NASA programs involving digital communications is considered. The system architecture and tradeoff analysis that led to the selection of the system to be simulated is presented

High Efficiency Power Amplifier Based on Envelope Elimination and Restoration Technique

Due to complex envelope and phase modulation employed in modern transmitters it is necessary to use power amplifiers that have high linearity. Linear power amplifiers (classes A, B and AB) are commonly used, but they suffer from low efficiency especially if the transmitted signal has high peak to average power ratio (PAPR). Kahn's technique based on envelope elimination and restoration (EER) is based on idea that high efficiency power supply (envelope amplifier) could be used to modulate the envelope of high efficient non linear power amplifiers (classes D or E). This paper presents solutions for power amplifier that performs envelope modulation and class E amplifier that is used as a non linear amplifier. The envelope amplifier is implemented as a multilevel converter in series with linear regulator and can provide up to 100 W of instantaneous power and reproduce 2 MHz sine wave. The implemented Class E amplifier can operate at 120 MHz with efficiency near to 85%. The envelope amplifier and class E amplifier have been integrated and efficiency and linearity of the implemented transmitter has been measured and presente

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications