Implementation Aspects of a Transmitted-Reference UWB Receiver

In this paper, we discuss the design issues of an ultra wide band (UWB) receiver targeting a single-chip CMOS implementation for low data-rate applications like ad hoc wireless sensor networks. A non-coherent transmitted reference (TR) receiver is chosen because of its small complexity compared to other architectures. After a brief recapitulation of the UWB fundamentals and a short discussion on the major differences between coherent and non-coherent receivers, we discuss issues, challenges and possible design solutions. Several simulation results obtained by means of a behavioral model are presented, together with an analysis of the trade-off between performance and complexity in an integrated circuit implementation

An imaging system for PLIF/Mie measurements for a combusting flow

The equipment required to establish an imaging system can be divided into four parts: (1) the light source and beam shaping optics; (2) camera and recording; (3) image acquisition and processing; and (4) computer and output systems. A pulsed, Nd:YAG-pummped, frequency-doubled dye laser which can freeze motion in the flowfield is used for an illumination source. A set of lenses is used to form the laser beam into a sheet. The induced fluorescence is collected by an UV-enhanced lens and passes through an UV-enhanced microchannel plate intensifier which is optically coupled to a gated solid state CCD camera. The output of the camera is simultaneously displayed on a monitor and recorded on either a laser videodisc set of a Super VHS VCR. This videodisc set is controlled by a minicomputer via a connection to the RS-232C interface terminals. The imaging system is connected to the host computer by a bus repeater and can be multiplexed between four video input sources. Sample images from a planar shear layer experiment are presented to show the processing capability of the imaging system with the host computer

A CMOS 0.18μm 64×64 single photon image sensor with in-pixel 11b time-to-digital converter

The design and characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital converter (TDC) is presented. It is targeted for time-resolved imaging, in particular 3D imaging. The achieved pixel pitch is 64μm with a fill factor of 3.5%. The chip was fabricated in a 0.18μm standard CMOS technology and implements a double functionality: Time-of-Flight estimation and photon counting. The imager features a programmable time resolution for the array of TDCs from 625ps down to 145ps. The measured accuracy of the minimum time bin is lower than ±1LSB DNL and 1.7LSB INL. The TDC jitter over the full dynamic range is less than 1LSB. Die-to-die process variation and temperature are discarded by auto-calibration. Fast quenching/restore circuit on each pixel lowers the power consumption by limiting the avalanche currents. Time gatedoperation is possible as well.Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad TEC2012-38921- C02, IPT- 2011-1625-430000, IPC- 20111009 CDTIJunta de Andalucía TIC 2012- 233

Networked VAX/LSI/CAMAC Data Acquisition System Development

Recent development of the Caltech data acquisition system installed in 1981, which runs on a VAX-11/750, a Peritek Q-bus network, LSI-11s, and CAMAC, is described. In this system, the DEC VMS and RT-11 operating systems are supported on the VAX "host" and LSI-11 "front-end" computers by a VMS device driver and network host program, and a bootable RT-11 device driver. Network "utility" and "control" programs provide general purpose support for communication between front-end and host software. Data acquisition software tools are provided for writing programs to run nuclear physics experiments. A system similar to Caltech's was installed at the University of Rochester in 1982. The network has been tested for speed and real-time response. After including all software overhead required by data acquisition, it was found that the system could transfer buffers and acknowledge their receipt at a net speed of 127 KB per second with a 35% load on the host computer. The network software is currently being rehosted on Ethernet hardware at Caltech in a multiple host - many front-end computer configuration. Compatibility with the current Peritek network software will be maintained

A NASA family of minicomputer systems, Appendix A

This investigation was undertaken to establish sufficient specifications, or standards, for minicomputer hardware and software to provide NASA with realizable economics in quantity purchases, interchangeability of minicomputers, software, storage and peripherals, and a uniformly high quality. The standards will define minicomputer system component types, each specialized to its intended NASA application, in as many levels of capacity as required