At-Speed Path Delay Test

This research describes an approach to test metastability of flip-flops with help of multiple at-speed capture cycles during delay test. K longest paths per flip-flop test patterns are generated, such that a long path on one clock cycle feeds a long path on the next clock cycle, and so on. Traditional structural delay tests do not test whether time borrowing or stealing is working correctly, since only a single at-speed cycle is tested. To detect path delay faults for the multi-cycle paths, it is necessary to start a path at a register and end at a register while passing through another register, testing the longest paths between each pair of registers. This requires three or more at-speed cycles, rather than the two of traditional Launch on Capture test. This produces power supply noise closer to functional mode, and permits the testing of flip-flop metastability and time-borrowing latches, that cannot be tested by any other structural test technique. The path generation algorithm uses the circuit structure, and then the paths are sequentially justified using Boolean Satisfiability algorithms. The algorithm has been implemented in C++ on an Intel Core i7 machine. Experiments have been performed on various ISCAS benchmark circuits in both robust and non-robust path generation technique to evaluate our approach

Individual flip-flops with gated clocks for low power datapaths

Energy consumption has become one of the important factors in digital systems, because of the requirement to dissipate this energy in high-density circuits and to extend the battery life in portable systems such as devices with wireless communication capabilities. Flip-flops are one of the most energy-consuming components of digital circuits. This paper presents techniques to reduce energy consumption by individually deactivating the clock when flip-flops do not have to change their value. Flip-flop structures are proposed and selection criteria given to obtain minimum energy consumption. The structures have been evaluated using energy models and validated by switch-level simulations. For the applications considered, significant energy reductions are achieved.Peer ReviewedPostprint (published version

A low-speed BIST framework for high-performance circuit testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addresse

Method and apparatus for a single channel digital communications system

A method and apparatus are described for synchronizing a received PCM communications signal without requiring a separate synchronizing channel. The technique provides digital correlation of the received signal with a reference signal, first with its unmodulated subcarrier and then with a bit sync code modulated subcarrier, where the code sequence length is equal in duration to each data bit

Digital computing cardiotachometer

A tachometer is described which instantaneously measures heart rate. During the two intervals between three succeeding heart beats, the electronic system: (1) measures the interval by counting cycles from a fixed frequency source occurring between the two beats; and (2) computes heat rate during the interval between the next two beats by counting the number of times that the interval count must be counted to zero in order to equal a total count of sixty times (to convert to beats per minute) the frequency of the fixed frequency source

Throughput-driven floorplanning with wire pipelining

The size of future high-performance SoC is such that the time-of-flight of wires connecting distant pins in the layout can be much higher than the clock period. In order to keep the frequency as high as possible, the wires may be pipelined. However, the insertion of flip-flops may alter the throughput of the system due to the presence of loops in the logic netlist. In this paper, we address the problem of floorplanning a large design where long interconnects are pipelined by inserting the throughput in the cost function of a tool based on simulated annealing. The results obtained on a series of benchmarks are then validated using a simple router that breaks long interconnects by suitably placing flip-flops along the wires

Fast scan control for deflection type mass spectrometers

A high speed scan device is reported that allows most any scanning sector mass spectrometer to measure preselected gases at a very high sampling rate. The device generates a rapidly changing staircase output which is applied to the accelerator of the spectrometer and it also generates defocusing pulses that are applied to one of the deflecting plates of the spectrometer which when shorted to ground deflects the ion beam away from the collector. A defocusing pulse occurs each time there is a change in the staircase output