2,950 research outputs found

    Fully Dynamic Effective Resistances

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    In this paper we consider the \emph{fully-dynamic} All-Pairs Effective Resistance problem, where the goal is to maintain effective resistances on a graph GG among any pair of query vertices under an intermixed sequence of edge insertions and deletions in GG. The effective resistance between a pair of vertices is a physics-motivated quantity that encapsulates both the congestion and the dilation of a flow. It is directly related to random walks, and it has been instrumental in the recent works for designing fast algorithms for combinatorial optimization problems, graph sparsification, and network science. We give a data-structure that maintains (1+ϵ)(1+\epsilon)-approximations to all-pair effective resistances of a fully-dynamic unweighted, undirected multi-graph GG with O~(m4/5ϵ4)\tilde{O}(m^{4/5}\epsilon^{-4}) expected amortized update and query time, against an oblivious adversary. Key to our result is the maintenance of a dynamic \emph{Schur complement}~(also known as vertex resistance sparsifier) onto a set of terminal vertices of our choice. This maintenance is obtained (1) by interpreting the Schur complement as a sum of random walks and (2) by randomly picking the vertex subset into which the sparsifier is constructed. We can then show that each update in the graph affects a small number of such walks, which in turn leads to our sub-linear update time. We believe that this local representation of vertex sparsifiers may be of independent interest

    Testability and redundancy techniques for improved yield and reliability of CMOS VLSI circuits

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    The research presented in this thesis is concerned with the design of fault-tolerant integrated circuits as a contribution to the design of fault-tolerant systems. The economical manufacture of very large area ICs will necessitate the incorporation of fault-tolerance features which are routinely employed in current high density dynamic random access memories. Furthermore, the growing use of ICs in safety-critical applications and/or hostile environments in addition to the prospect of single-chip systems will mandate the use of fault-tolerance for improved reliability. A fault-tolerant IC must be able to detect and correct all possible faults that may affect its operation. The ability of a chip to detect its own faults is not only necessary for fault-tolerance, but it is also regarded as the ultimate solution to the problem of testing. Off-line periodic testing is selected for this research because it achieves better coverage of physical faults and it requires less extra hardware than on-line error detection techniques. Tests for CMOS stuck-open faults are shown to detect all other faults. Simple test sequence generation procedures for the detection of all faults are derived. The test sequences generated by these procedures produce a trivial output, thereby, greatly simplifying the task of test response analysis. A further advantage of the proposed test generation procedures is that they do not require the enumeration of faults. The implementation of built-in self-test is considered and it is shown that the hardware overhead is comparable to that associated with pseudo-random and pseudo-exhaustive techniques while achieving a much higher fault coverage through-the use of the proposed test generation procedures. The consideration of the problem of testing the test circuitry led to the conclusion that complete test coverage may be achieved if separate chips cooperate in testing each other's untested parts. An alternative approach towards complete test coverage would be to design the test circuitry so that it is as distributed as possible and so that it is tested as it performs its function. Fault correction relies on the provision of spare units and a means of reconfiguring the circuit so that the faulty units are discarded. This raises the question of what is the optimum size of a unit? A mathematical model, linking yield and reliability is therefore developed to answer such a question and also to study the effects of such parameters as the amount of redundancy, the size of the additional circuitry required for testing and reconfiguration, and the effect of periodic testing on reliability. The stringent requirement on the size of the reconfiguration logic is illustrated by the application of the model to a typical example. Another important result concerns the effect of periodic testing on reliability. It is shown that periodic off-line testing can achieve approximately the same level of reliability as on-line testing, even when the time between tests is many hundreds of hours

    Analysis, testing, and evaluation of faulted and unfaulted Wye, Delta, and open Delta connected electromechanical actuators

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    Mathematical models capable of simulating the transient, steady state, and faulted performance characteristics of various brushless dc machine-PSA (power switching assembly) configurations were developed. These systems are intended for possible future use as primemovers in EMAs (electromechanical actuators) for flight control applications. These machine-PSA configurations include wye, delta, and open-delta connected systems. The research performed under this contract was initially broken down into the following six tasks: development of mathematical models for various machine-PSA configurations; experimental validation of the model for failure modes; experimental validation of the mathematical model for shorted turn-failure modes; tradeoff study; and documentation of results and methodology

    Linear-Space Approximate Distance Oracles for Planar, Bounded-Genus, and Minor-Free Graphs

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    A (1 + eps)-approximate distance oracle for a graph is a data structure that supports approximate point-to-point shortest-path-distance queries. The most relevant measures for a distance-oracle construction are: space, query time, and preprocessing time. There are strong distance-oracle constructions known for planar graphs (Thorup, JACM'04) and, subsequently, minor-excluded graphs (Abraham and Gavoille, PODC'06). However, these require Omega(eps^{-1} n lg n) space for n-node graphs. We argue that a very low space requirement is essential. Since modern computer architectures involve hierarchical memory (caches, primary memory, secondary memory), a high memory requirement in effect may greatly increase the actual running time. Moreover, we would like data structures that can be deployed on small mobile devices, such as handhelds, which have relatively small primary memory. In this paper, for planar graphs, bounded-genus graphs, and minor-excluded graphs we give distance-oracle constructions that require only O(n) space. The big O hides only a fixed constant, independent of \epsilon and independent of genus or size of an excluded minor. The preprocessing times for our distance oracle are also faster than those for the previously known constructions. For planar graphs, the preprocessing time is O(n lg^2 n). However, our constructions have slower query times. For planar graphs, the query time is O(eps^{-2} lg^2 n). For our linear-space results, we can in fact ensure, for any delta > 0, that the space required is only 1 + delta times the space required just to represent the graph itself

    Object search and retrieval in indoor environment using a Mobile Manipulator

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    Robots are increasingly viewed as service agents in offices and homes. In many countries where the average population is aging, robots can be used for elderly care. This Thesis explores one such possibility using a mobile manipulator robot. Such robots have a mobile base to move from one place to another and an arm to pick and place objects. This Thesis considers a problem where the mobile manipulator needs to search for an object in an environment and bring it to some location. The optimal object search is formulated in terms of the popular traveling salesman problem (TSP) that computes the optimal sequence in which the Robot can visit all the possible locations where the object can possibly be. Prior information about the more likely locations is brought in by scaling the edge-weight of the TSP graph through the probabilities of the location. The Thesis can combine the output of TSP with navigation and manipulation planning built on top of Robot Operating Systems (ROS) to build the complete object search and retrieval pipeline. The results of the Thesis are validated both in simulation and actual hardware experiments

    Optimal Intervention in Traffic Networks

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    We present an efficient algorithm to identify which edge should be improved in a traffic network to minimize the total travel time. Our main result is to show that it is possible to approximate the variation of total travel time obtained by changing the congestion coefficient of any given edge, by performing only local computations, without the need of recomputing the entire equilibrium flow. To obtain such a result, we reformulate our problem in terms of the effective resistance between two adjacent nodes and suggest a new approach to approximate such effective resistance. We then study the optimality of the proposed procedure for recurrent networks, and provide simulations over synthetic and real transportation networks
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