1,525 research outputs found
Calibration of DAC mismatch errors in sigma delta ADCs based on a sine-wave measurement
We present an offline calibration procedure to correct the nonlinearity due element mismatch in the digital-to-analog converter (DAC) of a multibit Sigma Delta-modulation A/D converter. The calibration uses a single measurement on a sinusoidal input signal, from which the DAC errors can be estimated. The main quality of the calibration method is that it can be implemented completely in the digital domain (or in software) and does not intervene in any way in the analog modulator circuit. This way, the technique is a powerful tool for verifying and debugging designs. Due to the simplicity of the method, it may be also a viable approach for factory calibration
Design of a Cost-Efficient Reconfigurable Pipeline ADC
Power budget is very critical in the design of battery-powered implantable biomedical instruments. High speed, high resolution and low power usually cannot be achieved at the same time. Therefore, a tradeoff must be made to compromise every aspect of those features. As the main component of the bioinstrument, high conversion rate, high resolution ADC consumes most of the power. Fortunately, based on the operation modes of the bioinstrument, a reconfigurable ADC can be used to solve this problem. The reconfigurable ADC will operate at 10-bit 40 MSPS for the diagnosis mode and at 8-bit 2.5 MSPS for the monitor mode. The ADC will be completely turned off if no active signal comes from sensors or if an off command is received from the antenna.
By turning off the sample hold stage and the first two stages of the pipeline ADC, a significant power saving is achieved. However, the reconfigurable ADC suffers from two drawbacks. First, the leakage signals through the extra off-state switches in the third stage degrade the performance of the data converter. This situation tends to be even worse for high speed and high-resolution applications. An interference elimination technique has been proposed in this work to solve this problem. Simulation results show a significant attenuation of the spurious tones. Moreover, the transistors in the OTA tend to operate in weak inversion region due to the scaling of the bias current. The transistor in subthreshold is very slow due to the small transit frequency. In order to get a better tradeoff between the transconductance efficiency and the transit frequency, reconfigurable OTAs and scalable bias technique are devised to adjust the operating point from weak inversion to moderate inversion.
The figure of merit of the reconfigurable ADC is comparable to the previously published conventional pipeline ADCs. For the 10-bit, 40 MSPS mode, the ADC attains a 56.9 dB SNDR for 35.4 mW power consumption. For the 8-bit 2.5 MSPS mode, the ADC attains a 49.2 dB SNDR for 7.9 mW power consumption. The area for the core layout is 1.9 mm2 for a 0.35 micrometer process
Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor
Due to the switch from CCD to CMOS technology, CMOS based image sensors have become
smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart
from the extensive set of applications requiring image sensors, the next technological
breakthrough in imaging would be to consolidate and completely shift the conventional CMOS
image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative
technology in the imaging field, allowing multiple silicon tiers with different functions to be
stacked on top of each other. The technology allows for an extreme parallelism of the pixel
readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked
image sensor, and the parallelism of the readout can remain constant at any spatial resolution of
the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor
array resolution.
The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked
image sensors, structured with parallel readout circuitries. The readout circuit’s key
requirements are low noise, speed, low-area (for higher parallelism), and low power.
A CMOS imaging review is presented through a short historical background, followed by the
description of the motivation, the research goals, and the work contributions. The fundamentals
of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features,
the essential building blocks, types of operation, as well as their physical characteristics and their
evaluation metrics. Following up on this, the document pays attention to the readout circuit’s
noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron
noise imagers. Lastly, the fabricated test CIS device performances are reported along with
conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future
work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores
CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que
requerem sensores de imagem, o prĂłximo salto tecnolĂłgico no ramo dos sensores de imagem Ă©
o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a
tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia
inovadora no campo dos sensores de imagem, permitindo vários planos de silĂcio com diferentes
funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um
paralelismo extremo na leitura dos sinais vindos da matriz de pĂxeis. AlĂ©m disso, num sensor de
imagem de planos de silĂcio empilhados, os circuitos de leitura estĂŁo posicionados debaixo da
matriz de pĂxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer
resolução espacial, permitindo assim atingir um extremo baixo ruĂdo e um alto debito de
imagens, virtualmente para qualquer resolução desejada.
O objetivo deste trabalho Ă© o de desenhar circuitos de leitura de coluna de muito baixo ruĂdo,
planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas
altamente paralelizadas. Os requisitos chave para os circuitos de leitura sĂŁo de baixo ruĂdo,
rapidez e pouca área utilizada, de forma a obter-se o melhor rácio.
Uma breve revisĂŁo histĂłrica dos sensores de imagem CMOS Ă© apresentada, seguida da
motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem
CMOS sĂŁo tambĂ©m abordados para expor as suas caracterĂsticas, os blocos essenciais, os tipos
de operação, assim como as suas caracterĂsticas fĂsicas e suas mĂ©tricas de avaliação. No
seguimento disto, especial atenção Ă© dada Ă teoria subjacente ao ruĂdo inerente dos circuitos de
leitura e dos conversores de coluna, servindo para identificar os possĂveis aspetos que dificultem
atingir a tĂŁo desejada performance de muito baixo ruĂdo. Por fim, os resultados experimentais
do sensor desenvolvido sĂŁo apresentados junto com possĂveis conjeturas e respetivas conclusões,
terminando o documento com o assunto de empilhamento vertical de camadas de silĂcio, junto
com o possĂvel trabalho futuro
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