4,429 research outputs found

    Trade-off analysis and design of a Hydraulic Energy Scavenger

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    In the last years there has been a growing interest in intelligent, autonomous devices for household applications. In the near future this technology will be part of our society; sensing and actuating will be integrated in the environment of our houses by means of energy scavengers and wireless microsystems. These systems will be capable of monitoring the environment, communicating with people and among each other, actuating and supplying themselves independently. This concept is now possible thanks to the low power consumption of electronic devices and accurate design of energy scavengers to harvest energy from the surrounding environment. In principle, an autonomous device comprises three main subsystems: an energy scavenger, an energy storage unit and an operational stage. The energy scavenger is capable of harvesting very small amounts of energy from the surroundings and converting it into electrical energy. This energy can be stored in a small storage unit like a small battery or capacitor, thus being available as a power supply. The operational stage can perform a variety of tasks depending on the application. Inside its application range, this kind of system presents several advantages with respect to regular devices using external energy supplies. They can be simpler to apply as no external connections are needed; they are environmentally friendly and might be economically advantageous in the long term. Furthermore, their autonomous nature permits the application in locations where the local energy grid is not present and allows them to be ‘hidden' in the environment, being independent from interaction with humans. In the present paper an energy-harvesting system used to supply a hydraulic control valve of a heating system for a typical residential application is studied. The system converts the kinetic energy from the water flow inside the pipes of the heating system to power the energy scavenger. The harvesting unit is composed of a hydraulic turbine that converts the kinetic energy of the water flow into rotational motion to drive a small electric generator. The design phases comprise a trade-off analysis to define the most suitable hydraulic turbine and electric generator for the energy scavenger, and an optimization of the components to satisfy the systems specification

    Frequency division multiple supply (FDMS) for fast-response power delivery

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    Traditional power delivery networks (PDN) to ASICs have a bandwidth that extends to about 100 kHz such that these PDNs respond with adequate speed and meet performance specifications if the transient load current changes at a rate slower than 100 kHz. As ASICs become more computationally powerful, not only does their current consumption go up, their current transients undergo relatively rapid slew, e.g., with a bandwidth exceeding 10 MHz. The bandwidth mismatch between the PDN and the current demand of the ASIC causes a substantial loss in efficiency. This disclosure describes a PDN comprising an ensemble of three or more power supplies optimized to differing frequency ranges. A power supply from the ensemble automatically kicks in when transient currents arise with a bandwidth that includes the frequency range of the power supply. Power is delivered across the entire ASIC bandwidth at optimal efficiency and with excellent transient response

    The STAR MAPS-based PiXeL detector

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    The PiXeL detector (PXL) for the Heavy Flavor Tracker (HFT) of the STAR experiment at RHIC is the first application of the state-of-the-art thin Monolithic Active Pixel Sensors (MAPS) technology in a collider environment. Custom built pixel sensors, their readout electronics and the detector mechanical structure are described in detail. Selected detector design aspects and production steps are presented. The detector operations during the three years of data taking (2014-2016) and the overall performance exceeding the design specifications are discussed in the conclusive sections of this paper

    A double-sided silicon micro-strip super-module for the ATLAS inner detector upgrade in the high-luminosity LHC

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    The ATLAS experiment is a general purpose detector aiming to fully exploit the discovery potential of the Large Hadron Collider (LHC) at CERN. It is foreseen that after several years of successful data-taking, the LHC physics programme will be extended in the so-called High-Luminosity LHC, where the instantaneous luminosity will be increased up to 5 × 1034 cm−2 s−1. For ATLAS, an upgrade scenario will imply the complete replacement of its internal tracker, as the existing detector will not provide the required performance due to the cumulated radiation damage and the increase in the detector occupancy. The current baseline layout for the new ATLAS tracker is an all-silicon-based detector, with pixel sensors in the inner layers and silicon micro-strip detectors at intermediate and outer radii. The super-module is an integration concept proposed for the strip region of the future ATLAS tracker, where double-sided stereo silicon micro-strip modules are assembled into a low-mass local support structure. An electrical super-module prototype for eight double-sided strip modules has been constructed. The aim is to exercise the multi-module readout chain and to investigate the noise performance of such a system. In this paper, the main components of the current super-module prototype are described and its electrical performance is presented in detail

    3D ICs: An Opportunity for Fully-Integrated, Dense and Efficient Power Supplies

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    International audienceWith 3D technologies, the in-package solution allows integrated, efficient and granular power supplies to be designed for multi-core processors. As the converter design obtains few benefits from the scaling, 3DIC allows the best technology to be chosen i.e. one which suits the DC-DC converter design. This paper evaluates the achievable power efficiency between on-die and in-package converters using a combination of active (28 and 65nm CMOS nodes) and passive (poly, MIM, vertical capacitor) layers. Based on the same load power consumption, on-die and in-package switched capacitor converters achieve 65% and 78% efficiency, respectively, in a 1mm 2 silicon area. An additional high density capacitance layer (100nF/mm 2) improves efficiency by more than 20 points in 65nm for the same surface which emphasizes the need for dedicated technology for better power management integration. This paper shows that in-package power management is a key alternative for fully-integrated, dense and efficient power supplies

    Evaluation and implementation of a 5-level hybrid DC-DC converter

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    In this work, a hybrid voltage regulator topology is analyzed, implemented, and evaluated. The common topologies of DC-DC converters have proven to be lacking in some aspects, such as integrability for buck converters, or maximum efficiency for switched-capacitor regulators. The hybrid topology tackles these shortcomings by combining the advantages of switched-capacitor and inductor-based voltage regulators. A 5-level buck converter is evaluated, implemented, and compared to other converter implementations using the same components. The 5-Level Buck converter can achieve 5 different levels, allowing it to cover 4 operation regions, each between 2 levels. Accordingly, it covers a wide range of output voltages. By reducing the voltage difference at the inductor input, the 5-level buck converter can use smaller inductor compared to both 3-level and conventional buck converters which makes it cheaper, smaller in size, and much more efficient. Simulations show proper functionality of the 5-Level topology, while putting restrictions on the inductor size, efficiency, and component footprint (or total converter area). A test PCB is implemented for verification of the functionality and experimental measurements show that for the same switching frequency and inductor size, the 5-level buck converter achieves up to 15% efficiency improvement over a conventional buck converter and a 3-level buck converter at certain output voltage ranges. Peak efficiency of 94% has been achieved by the 5-Level hybrid converter, which includes all external switching and conduction losses. The proposed hybrid topology proved to yield high conversion efficiency even in the face of component size limitations, which indicates potential benefit in using multilevel converters for several off-chip as well as on-chip applications
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