On the Nature of X-ray Variability in Ark 564

We use data from a recent long ASCA observation of the Narrow Line Seyfert 1 Ark 564 to investigate in detail its timing properties. We show that a thorough analysis of the time series, employing techniques not generally applied to AGN light curves, can provide useful information to characterize the engines of these powerful sources.We searched for signs of non-stationarity in the data, but did not find strong evidences for it. We find that the process causing the variability is very likely nonlinear, suggesting that variability models based on many active regions, as the shot noise model, may not be applicable to Ark 564. The complex light curve can be viewed, for a limited range of time scales, as a fractal object with non-trivial fractal dimension and statistical self-similarity. Finally, using a nonlinear statistic based on the scaling index as a tool to discriminate time series, we demonstrate that the high and low count rate states, which are indistinguishable on the basis of their autocorrelation, structure and probability density functions, are intrinsically different, with the high state characterized by higher complexity.Comment: 13 pages, 13 figures, accepted for publication in A&

Energy-based Self-attentive Learning of Abstractive Communities for Spoken Language Understanding

Abstractive community detection is an important spoken language understanding task, whose goal is to group utterances in a conversation according to whether they can be jointly summarized by a common abstractive sentence. This paper provides a novel approach to this task. We first introduce a neural contextual utterance encoder featuring three types of self-attention mechanisms. We then train it using the siamese and triplet energy-based meta-architectures. Experiments on the AMI corpus show that our system outperforms multiple energy-based and non-energy based baselines from the state-of-the-art. Code and data are publicly available.Comment: Update baseline

Integrated 2-D Optical Flow Sensor

I present a new focal-plane analog VLSI sensor that estimates optical flow in two visual dimensions. The chip significantly improves previous approaches both with respect to the applied model of optical flow estimation as well as the actual hardware implementation. Its distributed computational architecture consists of an array of locally connected motion units that collectively solve for the unique optimal optical flow estimate. The novel gradient-based motion model assumes visual motion to be translational, smooth and biased. The model guarantees that the estimation problem is computationally well-posed regardless of the visual input. Model parameters can be globally adjusted, leading to a rich output behavior. Varying the smoothness strength, for example, can provide a continuous spectrum of motion estimates, ranging from normal to global optical flow. Unlike approaches that rely on the explicit matching of brightness edges in space or time, the applied gradient-based model assures spatiotemporal continuity on visual information. The non-linear coupling of the individual motion units improves the resulting optical flow estimate because it reduces spatial smoothing across large velocity differences. Extended measurements of a 30x30 array prototype sensor under real-world conditions demonstrate the validity of the model and the robustness and functionality of the implementation

Test schedules for VLSI circuits having built-in test hardware

AbstractNumerous built-in test techniques exist for testing structures within a VLSI chip. In general these techniques deal with a repeated application of the following steps: (1) generate a test vector; (2) transmit it to the structure being tested; (3) process the test through the structure; (4) obtain the response from the structure; and (5) process the response. These steps constitute a test schema. Because these steps must be repeated for each test vector, it is possible that steps in processing one test vector can overlap those used in processing another vector. The manner of overlapping this testing process leads to the concept of a test schedule. In this paper we first present a model for built-in test techniques and for describing test schemas and schedules. We introduce the new concept of an I-path which is used to transfer data from one place in a circuit to another, without modifying the data. Finally results are presented describing how to create test schedules that minimizes the total testing time. Lower bounds on the minimal test time are also derived

Experiments with a Malkus-Lorenz water wheel: Chaos and Synchronization

We describe a simple experimental implementation of the Malkus-Lorenz water wheel. We demonstrate that both chaotic and periodic behavior is found as wheel parameters are changed in agreement with predictions from the Lorenz model. We furthermore show that when the measured angular velocity of our water wheel is used as an input signal to a computer model implementing the Lorenz equations, high quality chaos synchronization of the model and the water wheel is achieved. This indicates that the Lorenz equations provide a good description of the water wheel dynamics.Comment: 12 pages, 7 figures. The following article has been accepted by the American Journal of Physics. After it is published, it will be found at http://scitation.aip.org/ajp

Simplified vector-thread architectures for flexible and efficient data-parallel accelerators

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 165-170).This thesis explores a new approach to building data-parallel accelerators that is based on simplifying the instruction set, microarchitecture, and programming methodology for a vector-thread architecture. The thesis begins by categorizing regular and irregular data-level parallelism (DLP), before presenting several architectural design patterns for data-parallel accelerators including the multiple-instruction multiple-data (MIMD) pattern, the vector single-instruction multiple-data (vector-SIMD) pattern, the single-instruction multiple-thread (SIMT) pattern, and the vector-thread (VT) pattern. Our recently proposed VT pattern includes many control threads that each manage their own array of microthreads. The control thread uses vector memory instructions to efficiently move data and vector fetch instructions to broadcast scalar instructions to all microthreads. These vector mechanisms are complemented by the ability for each microthread to direct its own control flow. In this thesis, I introduce various techniques for building simplified instances of the VT pattern. I propose unifying the VT control-thread and microthread scalar instruction sets to simplify the microarchitecture and programming methodology. I propose a new single-lane VT microarchitecture based on minimal changes to the vector-SIMD pattern.(cont.) Single-lane cores are simpler to implement than multi-lane cores and can achieve similar energy efficiency. This new microarchitecture uses control processor embedding to mitigate the area overhead of single-lane cores, and uses vector fragments to more efficiently handle both regular and irregular DLP as compared to previous VT architectures. I also propose an explicitly data-parallel VT programming methodology that is based on a slightly modified scalar compiler. This methodology is easier to use than assembly programming, yet simpler to implement than an automatically vectorizing compiler. To evaluate these ideas, we have begun implementing the Maven data-parallel accelerator. This thesis compares a simplified Maven VT core to MIMD, vector-SIMD, and SIMT cores. We have implemented these cores with an ASIC methodology, and I use the resulting gate-level models to evaluate the area, performance, and energy of several compiled microbenchmarks. This work is the first detailed quantitative comparison of the VT pattern to other patterns. My results suggest that future data-parallel accelerators based on simplified VT architectures should be able to combine the energy efficiency of vector-SIMD accelerators with the flexibility of MIMD accelerators.by Christopher Francis Batten.Ph.D