Analysis and Design of Electrostatic Discharge Protection Devices and Circuits

An electrostatic discharge (ESD) is a spontaneous electrical current that flows between two objects at different electrical potentials. ESD currents can reach several amps and are typically in the order of tens of nanoseconds. Concerning microelectronics, on-chip protection against ESD events has become a main concern on the reliability of IC as dimensions continue to shrink. ESD currents could lead to on-chip voltages that are high enough to cause MOS gate oxide breakdown. ICs can thus be damaged by human handling, contact with machinery, packaging, board assembling, etc. The main goal of this study was to analyze the effectiveness of two-stage ESD protection circuits by means of mixed mode TCAD simulations. Two-dimensional device simulations were carried out using T-Suprem4 and Taurus-Medici software from Synopsis. Also, a TCAD input deck calibration for an NXP Semiconductors¿ proprietary 0.14m¿ CMOS technology was realized. In addition, two aspects on the transparency of ESD protections were studied. An excessive leakage problem found in a real product was analyzed in TCAD. Furthermore, a new approach for distributed ESD protection design for broadband applications is also discussed, resulting in improved RF performance.Pérez Monteagudo, JM. (2010). Analysis and Design of Electrostatic Discharge Protection Devices and Circuits. http://hdl.handle.net/10251/21061.Archivo delegad

Area Efficient Device Optimization for ESD Protection in High Speed Interface ICs

Electrostatic discharge (ESD) protection is considered as a vital step in integrated circuit (IC) manufacturing process. IC chips are unable to overcome the effects of transient events without adequate discharge protection. Recent trend in the industry has seen the incorporation of system level ESD protection within the IC chip. Incorporating system level on-chip ESD protection often increases cost, degrades circuit performance and consumes layout area which could otherwise be used for improving the circuit performance. These design challenges could be easily overcome if the parasitic components in a circuit were used for ESD protection. Despite the various design challenges, on-chip ESD protection is still desirable as it saves the area on the circuit board by eliminating the traditional ESD protection devices resulting in more compact circuits. Furthermore, using parasitic components while designing on-chip system level ESD protection can save layout area. In order to effectively implement this solution, a study on ESD events, protection circuits and high-speed ICs was carried out. Different types of ESD events and the different models pertaining to ESD events were studied and are discussed in detail. An overview of high-speed integrated circuits was also carried out with emphasis on the protection topologies that are commonly used. The ESD characteristics of parasitic PNP devices in rail-based ESD protection structure was then studied to summarize its viability as a protection circuit. The turn-on or breakdown voltage of the parasitic PNP is studied by technology computer aided design (TCAD) simulations performed in Silvaco software. The breakdown voltage, holding voltage, on resistance and failure current were studied and modeled to maximize ESD protection

Modeling an ESD Gun Discharge to a USB Cable

When an electrostatic discharge (ESD) gun discharges to a USB cable, the routing and quality of the cable impacts the waveform seen at the printed circuit board (PCB) connected to the cable and the ability of an on-board transient voltage suppressor (TVS) to protect sensitive electronics. The impact of cable configurations during ESD gun contact discharge tests was investigated for multiple cable configurations. Injection to a cable pin whose shield is \u27floating\u27 at the injection site can cause a double-peak in the ESD waveform at the PCB and a lower maximum stress level than when the cable shield is connected to the return plane. Poor shielding of the USB connector can further induce a pre-pulse effect, where a smaller ESD pulse arrives at the PCB before the main pulse. This pre-pulse can result in poor firing of the TVS device and thus worsen ESD stress at a sensitive IC. Circuit models were developed to anticipate and explain both of these phenomena. These models were incorporated into a system-level transient simulation including models of a PCB with a TVS and a pair of on-chip diodes. This system-level model was able to predict the quasi-static and peak voltages and currents at the on-chip diode during 1-8 kV ESD contact-discharge tests with various USB cable configurations to within less than 30%. These models were used to develop test and design guidelines to account for the impact of the quality and configuration of a USB cable during an ESD discharge

Optimization and modeling of ESD protection devices

“Transient voltage suppressors (TVS) are used to protect ICs (integrated circuits) against overvoltage, ESD (Electrostatic Discharge), inductive load switching, and even lightning strikes. In this research, a transient behavior model framework for ESD protection devices is used for modelling four different types of TVS (non-snapback, snapback, spark gap like device and varistor). The System-Efficient ESD Design (SEED) methodology is utilized to strengthen the trust in the model framework by efficient simulation of ESD interaction of the off-chip ESD protection devices with the IC ESD protection device and associated measurement data. Improvements in the TVS transient response, accounting for conductivity modulation, voltage overshot at the snapback voltage, etc., are required to accurately model the ESD protection device. With this in mind, the unimproved model is presented for various ESD protection device where their transient behavior of single component can be fully described by a quasistatic very fast transmission line pulse (VF)-TLP. The improved model is validated within a sub-system consisting of an off-chip ESD protection device, an IC on-chip protection and a PCB trace in between. Multiple solutions to avoid convergence issues are also proposed for effective simulation”--Abstract, page iv

SEED modeling of an ESD gun discharge to a USB cable

“An IC protected by a transient voltage suppression (TVS) diode may fail if the TVS device does not turn on or does not turn on quickly enough, causing the IC to take the full brunt of the electrostatic discharge (ESD) event. Transient simulation models have been developed for ESD protection devices for the purpose of system-efficient ESD design (SEED). The TVS modeling methodology has been improved to better represent the physics that occurs during the TVS response and more accurately predict the interactions between off-chip and on-chip protection devices. Moreover, a complicated test scenario -- an ESD gun discharge through a USB cable -- was investigated and simulated, to demonstrate the impact of position, grounding condition, and quality of the USB cable. Test and design guidelines are proposed for incorporating a USB cable in a contact-discharge ESD test. At the beginning, a hybrid simulation approach was proposed, which uses a full-wave model of the ESD gun, cable, and enclosure combined with the ESD protection devices and test board’s circuit-level models. The voltage and current of ESD protection devices are captured within 24-35% compared to the measurements, under various cable configurations. To further improve the simulation accuracy, physics-based modeling methodologies were proposed to improve the previously developed TVS model, especially on the falling edge after the overshoot. The ESD protection device’s response was studied in simulation and measurement for various cable configurations. And the overall discrepancy is within 30%. The modeling process can help engineers to evaluate the design effectiveness under various complicated test scenarios”--Abstract, page iv

Measurement and Analysis of Electromagnetic Field, Noise and IC Logic Error due to system-level ESD

Department of Electrical EngineeringAs the high performance very-large-scale integration (VLSI) systems operate with high speed and low voltage, the system-level electrostatic discharge (ESD) event is becoming one of the important noise sources causing logic errors and system malfunctions such as system reboot or fault. To understand the ESD noise phenomena and improve the system-level ESD noise immunity for devices, the accurate ESD noise measurement and analysis of IC logic errors are necessary. Section I is written for the tendency of ESD research and previous research. This paper presents the noise type correlation by measuring the signal-ground noise and power-ground noise simultaneously on the fundamental F/F operation circuit and shows the type of error from chip, in section II. Furthermore, the decoupling capacitors (de-cap) effect that can reduce the error occurrence by checking the error rate are analyzed. A generator is designed on the main board which is based on real operating laptop, and the chip on dual in-line memory module (DIMM) is also designed to perform the basic F/F operation. The clock and data input from generator are connected to the chip on the DIMM through the small outline dual in-line memory module (SODIMM) socket. ESD occurs at the corner of the ground plane of main board. The specification of the ESD generator satisfies IEC 61000-4-2 [1]. The ESD current flows along the ground strap, and affects the DIMM. IN-ground, CLK-ground, OUT-ground and power-ground on the DIMM are simultaneously measured to determine the effect of ESD on the main board. To analyze the error ratio according to the ESD voltage level, the voltage setup of the ESD gun is 3kV, 5kV and 8kV. To investigate the effects of chip shielding and DIMM de-caps on the error probability of DIMM, the experiment is conducted under the several conditions. After confirming the normal operation for each condition, the error type on the DIMM due to the ESD occurred in the circuit is analyzed and the statistics are shown. The results are verified by H-spice simulation, Vector Network Analyzer (VNA) and HFSS simulation. In order to obtain the improvement method of the DIMM immunity, experiments are conducted to find out the effective position and number of DIMM de-cap. Accurate measurements of electromagnetic fields are also essential to analyze the radiated noise due to unwanted electrostatic discharge (ESD) events at electronic devices. Usually, to know the radiated noise by ESD events, the voltages induced at field probes are measured, and the fields are obtained from the voltage by de-convolving the probe factor. In section ???, the two probe-factor deconvolution methods are investigated and compared in the measurements of the fields induced by system-level ESD events.ope

Design of an Apparatus for Experimental Validation of the Plasma Kinetic Model for Electrostatic Discharge

Electrostatic discharge (ESD) events are a serious safety concern when handling nuclear weapons. Current safety analysis operates under the assumption that sparks produced during threshold ESD events are overdriven and deliver all stored energy to a victim load. This assumption may result in safety procedures that are overly conservative unless a more accurate characterization can be made. Colorado School of Mines (CSM), in partnership with Los Alamos National Laboratory (LANL), has developed a plasma kinetic model for electrostatic discharge in COMSOL to model threshold ESD events from dielectric surfaces. The first experiment in a two experiment series aiming to validate this model involves quantifying the proportion of energy a target surface receives from a charged surface during a threshold ESD event. Experimental results will be compared to simulations run by CSM. This thesis covers the design of an experimental apparatus to be used in this first series of experiments.Mechanical Engineerin

Prototyping a Capacitive Sensing Device for Gesture Recognition

Capacitive sensing is a technology that can detect proximity and touch. It can also be utilized to measure position and acceleration of gesture motions. This technology has many applications, such as replacing mechanical buttons in a gaming device interface, detecting respiration rate without direct contact with the skin, and providing gesture sensing capability for rehabilitation devices. In this thesis, an approach to prototype a capacitive gesture sensing device using the Eagle PCB design software is demonstrated. In addition, this paper tested and evaluated the resulting prototype device, validating the effectiveness of the approach