Analog and mixed-signal circuitry for system-assisted high-speed I/O links

The state-of-the-art design methodology for high-speed I/O links is to specify component-level design requirements to achieve high-fidelity component-level performance. While designing each component in the link with high fidelity guarantees a reliable link, it does not inherently optimize the link for metrics such as the power, design complexity, or bit error rate performance. Recently, due to the increased demand for data bandwidth in backplane I/O, a system-assisted design methodology has been developed to optimize the system for a given set of metrics. By optimizing on the system level rather than the component level, the performance at the component level can be reduced from high quality to sufficient when the component is deployed within the I/O link. The new system-level design methodology encourages the utilization of novel circuit architectures. In this dissertation, novel analog and mixed-signal circuitry for system-assisted high-speed I/O links is presented. The novel circuitry expands upon traditional analog and mixed-signal circuit architectures in order to achieve system-level design goals and requirements without significant power or area overhead

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Dynamic input match correction in R.F. low noise amplifiers

An R.F. circuit that recognizes its faults, and then corrects its performance in real-time has been the holy-grail of RFIC design. This work presents, for the first time, a complete architecture and successful implementation of such a circuit. It is the first step towards the grand vision of fault-free, package independent, integrated R.F. Front End circuitry. The performance of R.F. front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input. These inductances have wide tolerances and are difficult to co-design for. A novel methodology, which overcomes current obstacles plaguing such an objective, is proposed wherein the affected performance metric of the circuit is quantified, and the appropriate design parameter is modified in real-time, thus enabling self-correction. This proof of concept is demonstrated by designing a cascode LNA and the complete self-correction circuit in IBM 0.25 µm CMOS RF process. The self-correction circuitry ascertains the input match frequency of the circuit by measuring its performance and determines the frequency interval by which it needs to be shifted to restore it to the desired value. It then feeds back a digital word to the LNA which adaptively corrects its input-match. It offers the additional flexibility of using different packages for the front-end since it renders the circuitry independent of package parasitics, by re-calibrating the input match on-the-fly. The circuitry presented in this work offers the advantages of low power, robustness, absence of DSP cores or processors, reduction in design cycle times, guaranteed optimal performance under varying conditions and fast correction times (less than 30 µs)

Ultra-low power, low-voltage transmitter at ISM band for short range transceivers

Tezin basılısı İstanbul Şehir Üniversitesi Kütüphanesi'ndedir.The increasing demand for technology to be used in every aspect of our lives has led the way to many new applications and communication standards. WSN and BAN are some of the new examples that utilize electronic circuit design in the form of very small sensors to perform their applications. They consist of small sensor nodes and have applications ranging from entertainment to medicine. Requirements such as decreasing the area and the power consumption help to have longer-lasting batteries and smaller devices. The standard paves the way for the devices from different vendors to communicate with each other, and that motivates us to make designs as compatible with the standard as it can be. In this thesis, an ultra-low power high efficient transmitter with a small area working at 2.4 GHz have been designed for BAN applications. A study on the system-view perspective is important in optimizing the area and power since the transmitter architecture can change the circuit design. From a circuit design perspective, seeking to decrease power consumption means thinking of new techniques to implement the same function or a new system. Inspired by new trends, this research presents a design solution to the previously mentioned problem and hopefully, after fabrication, the measured results will match the simulated results to prove the validity of the design.Declaration of Authorship ii Abstract iv Öz v Acknowledgments vii List of Figures x List of Tables xiii Abbreviations xiv 1 Introduction 1 1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Communication Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2.1 Digital Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.2 Unwanted Power Limitations . . . . . . . . . . . . . . . . . . . . . 3 1.2.3 Multiple Access Techniques . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Transmitter System Level Specifications . . . . . . . . . . . . . . . . . . . 4 1.3.1 Low Power Wireless Standards . . . . . . . . . . . . . . . . . . . . 4 1.4 Low-Power Wireless Transceiver systems . . . . . . . . . . . . . . . . . . . 6 1.4.1 Survey of the previous work . . . . . . . . . . . . . . . . . . . . . . 7 1.4.2 The Designed Transmitter System . . . . . . . . . . . . . . . . . . 8 1.5 Ultra-Low Power Transmitters Performance Metrics . . . . . . . . . . . . 9 1.6 Thesis Contribution and Outline . . . . . . . . . . . . . . . . . . . . . . . 10 2 Circuit Design for The Transmitter 11 2.1 Technology Characterization and Modeling for Low-Power Designs . . . 11 2.1.1 Passive Components modeling . . . . . . . . . . . . . . . . . . . . 11 2.1.2 Active Components Modeling . . . . . . . . . . . . . . . . . . . . . 13 2.1.3 MOS Transistor Sub-threshold Modeling . . . . . . . . . . . . . . 13 2.1.4 MOS Transistor Simulation-Based Modeling . . . . . . . . . . . . . 14 2.2 Low-Voltage Low-Power Analog and RF Design Principles . . . . . . . . . 17 2.2.1 Separate Gate Biasing of The Inverter . . . . . . . . . . . . . . . . 17 2.2.2 Body Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 Low-Voltage Analog Mixed Biasing Circuit Designs . . . . . . . . . . . . . 18 2.3.1 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.2 Operational Amplifier Design . . . . . . . . . . . . . . . . . . . . . 19 2.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.1 The MEMS Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.2 Crystal Oscillator Topologies . . . . . . . . . . . . . . . . . . . . . 23 2.4.3 Design of The CMOS Crystal Oscillator . . . . . . . . . . . . . . . 26 2.5 Pre-Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.6 OOK Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.7 BPSK Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8 Digital Control of the Modulators . . . . . . . . . . . . . . . . . . . . . . . 35 2.9 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.9.1 ULP PA Topologies Survey . . . . . . . . . . . . . . . . . . . . . . 38 2.9.2 The Push-Pull PA Design Methodology . . . . . . . . . . . . . . . 41 2.10 Transmit/Receive (T/R) Switch . . . . . . . . . . . . . . . . . . . . . . . 43 2.10.1 T/R Switch Topologies . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.10.2 Suggested Low-Area Low-Voltage RF Switch . . . . . . . . . . . . 46 3 Transmitter Integration and Final Results 48 3.1 Transmitter Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2 Transmitter Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3 Results Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.4 Results Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4 Conclusions 59 4.1 Thesis Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 A Bond Wire Parasitic Modeling 61 B Crystal Oscillator With Parasitic Effects 67 B.1 Simulation of FBAR with Parasitic Effects . . . . . . . . . . . . . . . . . 67 B.2 Root Locus Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Bibliography 7

Design and development of a CMOS power amplifier for digital applications

Master'sMASTER OF ENGINEERIN

Integrated Circuit Design for Hybrid Optoelectronic Interconnects

This dissertation focuses on high-speed circuit design for the integration of hybrid optoelectronic interconnects. It bridges the gap between electronic circuit design and optical device design by seamlessly incorporating the compact Verilog-A model for optical components into the SPICE-like simulation environment, such as the Cadence design tool. Optical components fabricated in the IME 130nm SOI CMOS process are characterized. Corresponding compact Verilog-A models for Mach-Zehnder modulator (MZM) device are developed. With this approach, electro-optical co-design and hybrid simulation are made possible. The developed optical models are used for analyzing the system-level specifications of an MZM based optoelectronic transceiver link. Link power budgets for NRZ, PAM-4 and PAM-8 signaling modulations are simulated at system-level. The optimal transmitter extinction ratio (ER) is derived based on the required receiver\u27s minimum optical modulation amplitude (OMA). A limiting receiver is fabricated in the IBM 130 nm CMOS process. By side- by-side wire-bonding to a commercial high-speed InGaAs/InP PIN photodiode, we demonstrate that the hybrid optoelectronic limiting receiver can achieve the bit error rate (BER) of 10-12 with a -6.7 dBm sensitivity at 4 Gb/s. A full-rate, 4-channel 29-1 length parallel PRBS is fabricated in the IBM 130 nm SiGe BiCMOS process. Together with a 10 GHz phase locked loop (PLL) designed from system architecture to transistor level design, the PRBS is demonstrated operating at more than 10 Gb/s. Lessons learned from high-speed PCB design, dealing with signal integrity issue regarding to the PCB transmission line are summarized

Low Power Skin Impedance Spectrometer

Non-invasive diagnosing is becoming a growing trend in the Medical Field, and as a result devices that do apply these non-invasive diagnoses must be developed. This project developed a medical device that measures the skin’s impedance and Phase accurately via Bluetooth graphs the results on a computer. The designed achieved is capable of measuring impedance from 200 to 3000 Ohms. This allows the project to be used for the following applications: BIA, pain sensing and diabetes diagnosis

High performance building blocks for wireless receiver: multi-stage amplifiers and low noise amplifiers

Different wireless communication systems utilizing different standards and for multiple applications have penetrated the normal people's life, such as Cell phone, Wireless LAN, Bluetooth, Ultra wideband (UWB) and WiMAX systems. The wireless receiver normally serves as the primary part of the system, which heavily influences the system performance. This research concentrates on the designs of several important blocks of the receiver; multi-stage amplifier and low noise amplifier. Two novel multi-stage amplifier typologies are proposed to improve the bandwidth and reduce the silicon area for the application where a large capacitive load exists. They were designed using AMI 0.5 m µ CMOS technology. The simulation and measurement results show they have the best Figure-of-Merits (FOMs) in terms of small signal and large signal performances, with 4.6MHz and 9MHz bandwidth while consuming 0.38mW and 0.4mW power from a 2V power supply. Two Low Noise Amplifiers (LNAs) are proposed, with one designed for narrowband application and the other for UWB application. A noise reduction technique is proposed for the differential cascode Common Source LNA (CS-LNA), which reduces the LNA Noise Figure (NF), increases the LNA gain, and improves the LNA linearity. At the same time, a novel Common Gate LNA (CG-LNA) is proposed for UWB application, which has better linearity, lower power consumption, and reasonable noise performance. Finally a novel practical current injection built-in-test (BIT) technique is proposed for the RF Front-end circuits. If the off-chip component Lg and Rs values are well controlled, the proposed technique can estimate the voltage gain of the LNA with less than 1dB (8%) error