A BIST solution for frequency domain characterization of analog circuits

This work presents an efficient implementation of a BIST solution for frequency characterization of analog systems. It allows a complete characterization in terms of magnitude and phase, including also harmonic distortion and offset measurements. Signal generation is performed using a modified filter, while response evaluation is based on 1storder ÓÄ modulation and very simple digital processing. The signal generator and the response analyzer have been implemented using the Switched-Capacitor (SC) technique in a standard 0.35ìm-3.3V CMOS technology. Both circuits have been separately validated, and an on-board prototype of the complete test system for frequency characterization has been implemented. Experimental results verify the functionality of the proposed approach, and a dynamic range of [email protected] (1MHz clock) has been demonstrated.Gobierno de España TEC2007-68072/MIC, TSI 020400- 2008-71Catrene European Project 2A105SR

Design, Commissioning and Performance of the PIBETA Detector at PSI

We describe the design, construction and performance of the PIBETA detector built for the precise measurement of the branching ratio of pion beta decay, pi+ -> pi0 e+ nu, at the Paul Scherrer Institute. The central part of the detector is a 240-module spherical pure CsI calorimeter covering 3*pi sr solid angle. The calorimeter is supplemented with an active collimator/beam degrader system, an active segmented plastic target, a pair of low-mass cylindrical wire chambers and a 20-element cylindrical plastic scintillator hodoscope. The whole detector system is housed inside a temperature-controlled lead brick enclosure which in turn is lined with cosmic muon plastic veto counters. Commissioning and calibration data were taken during two three-month beam periods in 1999/2000 with pi+ stopping rates between 1.3*E3 pi+/s and 1.3*E6 pi+/s. We examine the timing, energy and angular detector resolution for photons, positrons and protons in the energy range of 5-150 MeV, as well as the response of the detector to cosmic muons. We illustrate the detector signatures for the assorted rare pion and muon decays and their associated backgrounds.Comment: 117 pages, 48 Postscript figures, 5 tables, Elsevier LaTeX, submitted to Nucl. Instrum. Meth.

Comb-based WDM transmission at 10 Tbit/s using a DC-driven quantum-dash mode-locked laser diode

Chip-scale frequency comb generators have the potential to become key building blocks of compact wavelength-division multiplexing (WDM) transceivers in future metropolitan or campus-area networks. Among the various comb generator concepts, quantum-dash (QD) mode-locked laser diodes (MLLD) stand out as a particularly promising option, combining small footprint with simple operation by a DC current and offering flat broadband comb spectra. However, the data transmission performance achieved with QD-MLLD was so far limited by strong phase noise of the individual comb tones, restricting experiments to rather simple modulation formats such as quadrature phase shift keying (QPSK) or requiring hard-ware-based compensation schemes. Here we demonstrate that these limitations can be over-come by digital symbol-wise phase tracking algorithms, avoiding any hardware-based phase-noise compensation. We demonstrate 16QAM dual-polarization WDM transmission on 38 channels at an aggregate net data rate of 10.68 Tbit/s over 75 km of standard single-mode fiber. To the best of our knowledge, this corresponds to the highest data rate achieved through a DC-driven chip-scale comb generator without any hardware-based phase-noise reduction schemes

Testing high resolution SD ADC’s by using the noise transfer function

A new solution to improve the testability of high resolution SD Analogue to Digital Converters (SD ADC’s) using the quantizer input as test node is described. The theoretical basis for the technique is discussed and results from high level simulations for a 16 bit, 4th order, audio ADC are presented. The analysis demonstrates the potential to reduce the computational effort associated with test response analysis versus conventional techniques

A 300-800MHz Tunable Filter and Linearized LNA applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver

A multiband flexible RF-sampling receiver aimed at software-defined radio is presented. The wideband RF sampling function is enabled by a recently proposed discrete-time mixing downconverter. This work exploits a voltage-sensing LNA preceded by a tunable LC pre-filter with one external coil to demonstrate an RF-sampling receiver with low noise figure (NF) and high harmonic rejection (HR). The second-order LC filter provides voltage pre-gain and attenuates the source noise aliasing, and it also improves the HR ratio of the sampling downconverter. The LNA consists of a simple amplifier topology built from inverters and resistors to improve the third-order nonlinearity via an enhanced voltage mirror technique. The RF-sampling receiver employs 8 times oversampling covering 300 to 800 MHz in two RF sub-bands. The chip is realized in 65 nm CMOS and the measured gain across the band is between 22 and 28 dB, while achieving a NF between 0.8 to 4.3 dB. The IIP2 varies between +38 and +49 dBm and the IIP3 between -14 dBm and -9 dBm, and the third and fifth order HR ratios are more than 60 dB. The LNA and downconverter consumes 6 mW, and the clock generator takes 12 mW at 800 MHz RF.\ud \u

Integrated phased array systems in silicon

Silicon offers a new set of possibilities and challenges for RF, microwave, and millimeter-wave applications. While the high cutoff frequencies of the SiGe heterojunction bipolar transistors and the ever-shrinking feature sizes of MOSFETs hold a lot of promise, new design techniques need to be devised to deal with the realities of these technologies, such as low breakdown voltages, lossy substrates, low-Q passives, long interconnect parasitics, and high-frequency coupling issues. As an example of complete system integration in silicon, this paper presents the first fully integrated 24-GHz eight-element phased array receiver in 0.18-μm silicon-germanium and the first fully integrated 24-GHz four-element phased array transmitter with integrated power amplifiers in 0.18-μm CMOS. The transmitter and receiver are capable of beam forming and can be used for communication, ranging, positioning, and sensing applications

System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system