A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices

Scalable Analysis, Verification and Design of IC Power Delivery

Due to recent aggressive process scaling into the nanometer regime, power delivery network design faces many challenges that set more stringent and specific requirements to the EDA tools. For example, from the perspective of analysis, simulation efficiency for large grids must be improved and the entire network with off-chip models and nonlinear devices should be able to be analyzed. Gated power delivery networks have multiple on/off operating conditions that need to be fully verified against the design requirements. Good power delivery network designs not only have to save the wiring resources for signal routing, but also need to have the optimal parameters assigned to various system components such as decaps, voltage regulators and converters. This dissertation presents new methodologies to address these challenging problems. At first, a novel parallel partitioning-based approach which provides a flexible network partitioning scheme using locality is proposed for power grid static analysis. In addition, a fast CPU-GPU combined analysis engine that adopts a boundary-relaxation method to encompass several simulation strategies is developed to simulate power delivery networks with off-chip models and active circuits. These two proposed analysis approaches can achieve scalable simulation runtime. Then, for gated power delivery networks, the challenge brought by the large verification space is addressed by developing a strategy that efficiently identifies a number of candidates for the worst-case operating condition. The computation complexity is reduced from O(2^N) to O(N). At last, motivated by a proposed two-level hierarchical optimization, this dissertation presents a novel locality-driven partitioning scheme to facilitate divide-and-conquer-based scalable wire sizing for large power delivery networks. Simultaneous sizing of multiple partitions is allowed which leads to substantial runtime improvement. Moreover, the electric interactions between active regulators/converters and passive networks and their influences on key system design specifications are analyzed comprehensively. With the derived design insights, the system-level co-design of a complete power delivery network is facilitated by an automatic optimization flow. Results show significant performance enhancement brought by the co-design

Power Semiconductors for An Energy-Wise Society

This IEC White Paper establishes the critical role that power semiconductors play in transitioning to an energy wise society. It takes an in-depth look at expected trends and opportunities, as well as the challenges surrounding the power semiconductors industry. Among the significant challenges mentioned is the need for change in industry practices when transitioning from linear to circular economies and the shortage of skilled personnel required for power semiconductor development. The white paper also stresses the need for strategic actions at the policy-making level to address these concerns and calls for stronger government commitment, policies and funding to advance power semiconductor technologies and integration. It further highlights the pivotal role of standards in removing technical risks, increasing product quality and enabling faster market acceptance. Besides noting benefits of existing standards in accelerating market growth, the paper also identifies the current standardization gaps. The white paper emphasizes the importance of ensuring a robust supply chain for power semiconductors to prevent supply-chain disruptions like those seen during the COVID-19 pandemic, which can have widespread economic impacts.The white paper highlights the importance of inspiring young professionals to take an interest in power semiconductors and power electronics, highlighting the potential to make a positive impact on the world through these technologies.The white paper concludes with recommendations for policymakers, regulators, industry and other IEC stakeholders for collaborative structures and accelerating the development and adoption of standards

Energy challenges for ICT

The energy consumption from the expanding use of information and communications technology (ICT) is unsustainable with present drivers, and it will impact heavily on the future climate change. However, ICT devices have the potential to contribute signi - cantly to the reduction of CO2 emission and enhance resource e ciency in other sectors, e.g., transportation (through intelligent transportation and advanced driver assistance systems and self-driving vehicles), heating (through smart building control), and manu- facturing (through digital automation based on smart autonomous sensors). To address the energy sustainability of ICT and capture the full potential of ICT in resource e - ciency, a multidisciplinary ICT-energy community needs to be brought together cover- ing devices, microarchitectures, ultra large-scale integration (ULSI), high-performance computing (HPC), energy harvesting, energy storage, system design, embedded sys- tems, e cient electronics, static analysis, and computation. In this chapter, we introduce challenges and opportunities in this emerging eld and a common framework to strive towards energy-sustainable ICT

Transmission and Distribution Co-Simulation and Applications

As the penetration of flexible loads and distributed energy resources (DERs) increases in distribution networks, demand dispatch schemes need to consider the effects of large-scale load control on distribution grid reliability. Thus, we need demand dispatch schemes that actively ensure that distribution grid operational constraints are network-admissible and still deliver valuable market services. In this context, this work develops and evaluates the performance of a new network-admissible version of the device-driven demand dispatch scheme called Packetized Energy Management (PEM). Specifically, this work develops and investigates the live grid constraint-based coordinator and metrics for performance evaluation. The effects of grid measurements for a practical-sized, 2,522-bus, unbalanced distribution test feeder with a 3000 flexible kW-scale loads operating under the network-admissible PEM scheme is discussed. The results demonstrate the value of live grid measurements in managing distribution grid operational constraints while PEM can effectively deliver frequency regulation services. Increased penetration of flexible loads and DERs on distribution system (DS) will lead to increased interaction of transmission and distribution (T&D) system operators to ensure reliable operation of the interconnected power grids, as well as the control actions at LV/MV grid in aggregation will have significant impact on the transmission systems (TS). Thus, a need arises to study the coupling of the transmission and distribution (T&D) systems. Therefore, this work develops a co-simulation platform based on decoupled approach to study integrated T&D systems collectively. Additionally, the results of a decoupled method applied for solving T&D power flow co-simulation is benchmarked against the collaborator developed unified solution which proves the accuracy of the decoupled approach. The existing approaches in the literature to study steady-state interaction of TS-DS have several shortcomings including that the existing methods exhibit scalability, solve-time and computational memory usage concerns. In this regard, this work develops comprehensive mathematical models of T&D systems for integrated power flow analysis and brings advancements from the algorithmic perspective to efficiently solve large-scale T&D circuits. Further, the models are implemented in low-cost CPU-GPU hybrid computing platform to further speed up the computational performance. The efficacy of the proposed models, solution algorithms, and their hardware implementation are demonstrated with more than 13,000 nodes using an integrated system that consists of 2383-bus Polish TS and multiple instances of medium voltage part of the IEEE 8,500-node DS. Case studies demonstrate that the proposed approach is scalable and can provide more than tenfold speed up on the solve time of very large-scale integrated T&D systems. Overall, this work develops practically applicable and efficient demand dispatch coordinator able to integrate DERs into DS while ensuring the grid operational constraints are not violated. Additionally, the dynamics introduced in the DS with such integration that travels to TS is also studied collectively using integrated T&D co-simulation and in the final step, a mathematically comprehensive model tackles the scalability, solve-time and computational memory usage concerns for large scale integrated T&D co-simulation and applications

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1

The impact of design techniques in the reduction of power consumption of SoCs Multimedia

Orientador: Guido Costa Souza de AraújoDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de ComputaçãoResumo: A indústria de semicondutores sempre enfrentou fortes demandas em resolver problema de dissipação de calor e reduzir o consumo de energia em dispositivos. Esta tendência tem sido intensificada nos últimos anos com o movimento de sustentabilidade ambiental. A concepção correta de um sistema eletrônico de baixo consumo de energia é um problema de vários níveis de complexidade e exige estratégias sistemáticas na sua construção. Fora disso, a adoção de qualquer técnica de redução de energia sempre está vinculada com objetivos especiais e provoca alguns impactos no projeto. Apesar dos projetistas conheçam bem os impactos de forma qualitativa, as detalhes quantitativas ainda são incógnitas ou apenas mantidas dentro do 'know-how' das empresas. Neste trabalho, de acordo com resultados experimentais baseado num plataforma de SoC1 industrial, tentamos quantificar os impactos derivados do uso de técnicas de redução de consumo de energia. Nos concentramos em relacionar o fator de redução de energia de cada técnica aos impactos em termo de área, desempenho, esforço de implementação e verificação. Na ausência desse tipo de dados, que relacionam o esforço de engenharia com as metas de consumo de energia, incertezas e atrasos serão frequentes no cronograma de projeto. Esperamos que este tipo de orientações possam ajudar/guiar os arquitetos de projeto em selecionar as técnicas adequadas para reduzir o consumo de energia dentro do alcance de orçamento e cronograma de projetoAbstract: The semiconductor industry has always faced strong demands to solve the problem of heat dissipation and reduce the power consumption in electronic devices. This trend has been increased in recent years with the action of environmental sustainability. The correct conception of an electronic system for low power consumption is an issue with multiple levels of complexities and requires systematic approaches in its construction. However, the adoption of any technique for reducing the power consumption is always linked with some specific goals and causes some impacts on the project. Although the designers know well that these impacts can affect the design in a quality aspect, the quantitative details are still unkown or just be kept inside the company's know-how. In this work, according to the experimental results based on an industrial SoC2 platform, we try to quantify the impacts of the use of low power techniques. We will relate the power reduction factor of each technique to the impact in terms of area, performance, implementation and verification effort. In the absence of such data, which relates the engineering effort to the goals of power consumption, uncertainties and delays are frequent. We hope that such guidelines can help/guide the project architects in selecting the appropriate techniques to reduce the power consumption within the limit of budget and project scheduleMestradoCiência da ComputaçãoMestre em Ciência da Computaçã