On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations

page number: 12International audienceWith the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of non-compliance becomes critical for circuit designers. However, on-chip characterization of noise is still necessary for model validation and design optimization. Although different on-chip measurement solutions have been proposed for emission issue characterization, no on-chip measurement methods have been proposed to address the susceptibility issues. This paper presents an on-chip noise sensor dedicated to the study of circuit susceptibility to electromagnetic interferences. A demonstration of the sensor measurement performances and benefits is proposed through a study of the susceptibility of a digital core to conducted interferences. Sensor measurements ensure a better characterization of actual coupling of interferences within the circuit and a diagnosis of failure origins

On-die signal integrity monitoring of gigabit serial I/Os

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (leaves 93-94).This thesis describes an embedded undersampling system for capturing analog wave-forms and monitoring signal integrity throughout a signal path. It is intended for use in Gigabit serial products, such as crosspoints and other networking products. Design reuse and simple components were the most important design parameters. The system has a small layout, a simple digital interface, and does not require a separate sample-and--hold circuit. The final system has 15 mV minimum resolution, operates over common-mode logic signals from 1.8V to 1.4V, and accurately captures signals up to 2GHz.by Alexander Wyatt Moore.M.Eng

Precise Timing of Digital Signals: Circuits and Applications

With the rapid advances in process technologies, the performance of state-of-the-art integrated circuits is improving steadily. The drive for higher performance is accompanied with increased emphasis on meeting timing constraints not only at the design phase but during device operation as well. Fortunately, technology advancements allow for even more precise control of the timing of digital signals, an advantage which can be used to provide solutions that can address some of the emerging timing issues. In this thesis, circuit and architectural techniques for the precise timing of digital signals are explored. These techniques are demonstrated in applications addressing timing issues in modern digital systems. A methodology for slow-speed timing characterization of high-speed pipelined datapaths is proposed. The technique uses a clock-timing circuit to create shifted versions of a slow-speed clock. These clocks control the data flow in the pipeline in the test mode. Test results show that the design provides an average timing resolution of 52.9ps in 0.18μm CMOS technology. Results also demonstrate the ability of the technique to track the performance of high-speed pipelines at a reduced clock frequency and to test the clock-timing circuit itself. In order to achieve higher resolutions than that of an inverter/buffer stage, a differential (vernier) delay line is commonly used. To allow for the design of differential delay lines with programmable delays, a digitally-controlled delay-element is proposed. The delay element is monotonic and achieves a high degree of transfer characteristics' (digital code vs. delay) linearity. Using the proposed delay element, a sub-1ps resolution is demonstrated experimentally in 0.18μm CMOS. The proposed delay element with a fixed delay step of 2ps is used to design a high-precision all-digital phase aligner. High-precision phase alignment has many applications in modern digital systems such as high-speed memory controllers, clock-deskew buffers, and delay and phase-locked loops. The design is based on a differential delay line and a variation tolerant phase detector using redundancy. Experimental results show that the phase aligner's range is from -264ps to +247ps which corresponds to an average delay step of approximately 2.43ps. For various input phase difference values, test results show that the difference is reduced to less than 2ps at the output of the phase aligner. On-chip time measurement is another application that requires precise timing. It has applications in modern automatic test equipment and on-chip characterization of jitter and skew. In order to achieve small conversion time, a flash time-to-digital converter is proposed. Mismatch between the various delay comparators limits the time measurement precision. This is demonstrated through an experiment in which a 6-bit, 2.5ps resolution flash time-to-digital converter provides an effective resolution of only 4-bits. The converter achieves a maximum conversion rate of 1.25GSa/s

On-Chip Power Supply Noise: Scaling, Suppression and Detection

Design metrics such as area, timing and power are generally considered as the primary criteria in the design of modern day circuits, however, the minimization of power supply noise, among other noise sources, is appreciably more important since not only can it cause a degradation in these parameters but can cause entire chips to fail. Ensuring the integrity of the power supply voltage in the power distribution network of a chip is therefore crucial to both building reliable circuits as well as preventing circuit performance degradation. Power supply noise concerns, predicted over two decades ago, continue to draw significant attention, and with present CMOS technology projected to keep on scaling, it is shown in this work that these issues are not expected to diminish. This research also considers the management and on-chip detection of power supply noise. There are various methods of managing power supply noise, with the use of decoupling capacitors being the most common technique for suppressing the noise. An in-depth analysis of decap structures including scaling effects is presented in this work with corroborating silicon results. The applicability of various decaps for given design constraints is provided. It is shown that MOS-metal hybrid structures can provide a significant increase in capacitance per unit area compared to traditional structures and will continue to be an important structure as technology continues to scale. Noise suppression by means of current shifting within the clock period of an ALU block is further shown to be an additional method of reducing the minimum voltage observed on its associated supply. A simple, and area and power efficient technique for on-chip supply noise detection is also proposed

Electroencephalogram signal acquisition in unshielded noisy environment

Researchers have used electroencephalography (EEG) as a window into the activities of the brain. High temporal resolution coupled with relatively low cost compares favourably to other neuroimaging techniques such as magnetoencephalography (MEG). For many years silver metal electrodes have been used for non-invasive monitoring electrical activities of the brain. Although these electrodes provide a reliable method for recording EEG they suffer from noise, such as offset potentials and drifts, and usability issues, e.g. skin prepa- ration and short circuiting of adjacent electrodes due to gel running. Low frequency noise performance is the key indicator in determining the signal to noise ratio of an EEG sensor. In order to tackle these issues a prototype Electric Potential Sensor (EPS) device based on an auto-zero operational amplifier has been developed and evaluated. The absence of 1/f noise in these devices makes them ideal for use with signal frequencies ~10Hz or less. The EPS is a novel active electrode electric potential sensor with ultrahigh input impedance. The active electrodes are designed to be physically and electrically robust and chemically and biochemically inert. They are electrically insulated (anodized) and scalable. These sensors are designed to be immersed in alcohol for sterilization purposes. A comprehensive study was undertaken to compare the results of EEG signals recorded by the EPS with different commercial systems. These studies comprised measurements of both free running EEG and Event Related Potentials. Strictly comparable signals were observed with cross correlations of higher than 0.9 between the EPS and other systems

Fabrication and High Speed Optoelectronic Characterization of Semiconductor Devices

This work is an investigation on the use of high speed optoelectronic techniques for the characterization of semiconductor devices. A low-frequency electrooptic probe station was demonstrated as well as the optoelectronic sampling scheme. The optoelectronic sampling technique relies on fast photoconductive switches for its operation. The autocorrelation signal detected in optoelectronic sampling was compared with signal detection by conventional techniques employing a sampling oscilloscope and a network analyser. The optoelectronic techniques described in this work depend critically on short-pulse lasers for the measurement of high speed devices. A fibre-grating pulse compressor was set-up to shorten the 120 ps pulses produced by a mode-locked Nd:YAG laser. Compression by a factor of 40 was demonstrated and nearly transform limited pulses of 3 ps duration were obtained. However, the output of the pulse compressor is very noisy and the output power is not high enough to enable electrooptic sampling experiments, in a jitter-free scheme. The same Nd:YAG laser was frequency doubled and used to synchronously pump a rhodamine 6G dye laser. Autocorrelation measurements obtained with the dye laser are again, very noisy and with poor reproducibility. The noise problems with the pulse compressor and with the dye laser were traced back to the Nd:YAG pump laser. It is concluded that this laser should be avoided as the source of short pulses for the electrooptic and optoelectronic measurement techniques. The use of a feedback loop is likely to reduce the noise in this laser, but drift in the intensity in a long time scale would still be present. A mode-locked Ti:Sapphire laser was also used for measurements in this project. Autocorrelation measurements taken with this laser are totally reproducible and contain little or no noise. The devices measured in this project were made by a combination of electron-beam lithography and photolithography. The use of these two lithography techniques together was made possible by the design of a mask set with alignment marks which can be used for registration in a mask aligner and in the electron beam lithography machine. Discrete devices were made and characterized by electrical techniques. Fabrication procedures were developed for resistors, Metal-Insulator-Metal (MIM) capacitors and for the Optoelecttonic Sampling Device (OSD). Discrete Mesfets were fabricated on MBE grown epilayers and their I-V characteristics were measured. A simplified optoelectronic sampling device was designed and made in a single lithographic step. It provides a quick way of producing devices in which autocorrelation measurements can be performed to determine the carrier lifetime in the substrate material. The optoelectronic sampling devices were made on four different substrate materials. The first one is a high purity, MBE grown GaAs epilayer, with very long lifetime (2ns). The control samples were made on "standard" semi-insulating GaAs, whose carrier lifetime is ~200 ps. Proton implantation in some of these devices made on SI GaAs substrate was used as a means of shortening the carrier lifetime, to produce fast turn-off times in the photoconductive switches. The lifetime after implantation of 4 x 10e14 protons/cm2 was estimated from an optoelectronic sampling measurement, to be around 40 ps. This is still a very long lifetime for the photoconductive switches. It is thought that self-annealing of the deep electron traps, caused by the lack of temperature control in the implanter, prevented the achievement of short lifetime in the switches. GaAs epilayers were grown by MBE at a temperature around 25

A time-based approach for multi-GHz embedded mixed-signal characterization and measurement /

The increasingly more sophisticated systems that are nowadays implemented on a single chip are placing stringent requirements on the test industry. New test strategies, equipment, and methodologies need to be developed to sustain the constant increase in demand for consumer and communication electronics. Techniques for built-in-self-test (BIST) and design-for-test (DFT) strategies have been proven to offer more feasible and economical testing solutions.Previous works have been conducted to perform on-chip testing, characterization, and measurement of signals and components. The current thesis advances those techniques on many levels. In terms of performance, an increase of more than an order of magnitude in speed is achieved. 70-GHz (effective sampling) on-chip oscilloscope is reported, compared to 4-GHz and 10-GHz ones in previous state-of-the-art implementations. Power dissipation is another area where the proposed work offer a superior solution compared to previous alternatives. All the proposed circuits do not exceed a few milliWatts of power dissipation, while performing multi-GHz high-speed signal capture at a medium resolution. Finally, and possibly most importantly, all the proposed circuits for test rely on a different form of signal processing; the time-based approach. It is believed that this approach paves the path to a lot of new techniques and circuit design skills that can be investigated more deeply. As an integral part of the time-based processing approach for GHz signal capture, this thesis verifies the advantages of using time amplification. The use of such amplification in the time domain is materialized with experimental results from three specific integrated circuits achieving different tasks in GHz high-speed in-situ signal measurement and characterization. Advantages of using such time-based approach techniques, when combined with the use of a front-end time amplifier, include noise immunity, the use of synthesizable digital cells, and circuit building blocks that track the technology scaling in terms of area and speed

Study of substrate noise and techniques for minimization

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (p. 155-158).This thesis presents a study of the effects of substrate noise on analog circuits in mixed-signal chips and techniques for minimizing these harmful effects on sensitive analog circuits. A microchip built in a 0.25um CMOS epitaxial process was designed, fabricated, and tested for this research. Through the use of an on-chip sampling scope, the effect of substrate noise generated by digital inverters with coupling capacitors to the substrate on analog circuits was characterized. Substrate noise coupled into a representative analog circuit, a switched capacitor delta-sigma modulator primarily through the asymmetrical parasitics of the input sampling circuit. Furthermore, since some of the parasitics are nonlinear with input voltage, substrate noise couples into the analog circuits producing an input signal dependent component and an input signal independent component. The substrate noise, with decay time constants of a few nanoseconds and ringing frequencies of few hundred megahertz, can decrease analog circuit performance. In the case of a delta-sigma modulator, substrate noise caused the signal to noise power ratio to decrease by more than 18dB, 3 bits in terms of analog-to-digital converter metrics. In addition, two techniques of minimizing the substrate noise and its effects were explored. The first used a replica delta-sigma modulator on the same chip to subtract the effects of substrate noise from the original delta-sigma modulator. This method proved useful for removing input signal independent substrate noise, but not input signal dependent substrate noise which dominates in-band noise for large input signal magnitudes. The second technique involved an active substrate noise cancellation system.(cont.) A discrete time feedback loop senses the substrate noise, processes it through a filter, and uses an array of digital inverters to cancel the substrate noise. The principal advantages of this technique are the shaping of substrate noise through a designed filter without a significant power penalty and design independence from the analog and digital components. Measured data shows that this technique is capable of over 20dB reduction in substrate noise on the substrate voltage itself. Measured data also shows over 10dB improvement in SNDR of the delta-sigma modulator in certain cases.by Mark Shane Peng.Ph.D