High performances monolithic CMOS detectors for space applications

During the last 10 years, research about CMOS image sensors (also called APS -Active Pixel Sensors) has been intensively carried out, in order to offer an alternative to CCDs as image sensors. This is particularly the case for space applications as CMOS image sensors feature characteristics which are obviously of interest for flight hardware: parallel or semi-parallel architecture, on chip control and processing electronics, low power dissipation, high level ofradiation tolerance... Many image sensor companies, institutes and laboratories have demonstrated the compatibility of CMOS image sensors with consumer applications: micro-cameras, video-conferencing, digital-still cameras. And recent designs have shown that APS is getting closer to the CCD in terms ofperformance level. However, the large majority ofthe existing products do not offer the specific features which are required for many space applications. ASTRI1JM and SUPAERO/CIMI have decided to work together in view of developing CMOS image sensors dedicated to space business. After a brief presentation of the team organisation for space image sensor design and production, the latest results of a high performances 512x512 pixels CMOS device characterisation are presented with emphasis on the achieved electro-optical performance. Finally, the on going and short-term coming activities of the team are discussed

Development of high-performances monolithic CMOS detectors for space applications

This paper describes the development of a 750x750 pixels CMOS image sensor for star tracker applications. A first demonstrator of such a star tracker called SSM star tracker built around a 512x512 detector has been recently developed and proves the feasibility of such instrument. In order to take fully advantage of the CMOS image sensor step, the 750x750 device called SSM CMOS detector which will take part of the final star tracker, can be considered as a major technical breakthrough that gives a decisive advantage in terms of on satellite implementation cost and flexibility (sensor mass and power consumption minimisation, electronics and architecture flexibility). Indeed, built using the 0.5μm Alcatel Microelectronics standard CMOS technology, the SSM CMOS detector will feature on-chip temperature sensor and on-chip sequencer. In order to evaluate the radiation tolerance of such manufacturing technology, a radiation campaign that contains studies of total dose and latch-up effects has been led on a specific test vehicle

Trends in Pixel Detectors: Tracking and Imaging

For large scale applications, hybrid pixel detectors, in which sensor and read-out IC are separate entities, constitute the state of the art in pixel detector technology to date. They have been developed and start to be used as tracking detectors and also imaging devices in radiography, autoradiography, protein crystallography and in X-ray astronomy. A number of trends and possibilities for future applications in these fields with improved performance, less material, high read-out speed, large radiation tolerance, and potential off-the-shelf availability have appeared and are momentarily matured. Among them are monolithic or semi-monolithic approaches which do not require complicated hybridization but come as single sensor/IC entities. Most of these are presently still in the development phase waiting to be used as detectors in experiments. The present state in pixel detector development including hybrid and (semi-)monolithic pixel techniques and their suitability for particle detection and for imaging, is reviewed.Comment: 10 pages, 15 figures, Invited Review given at IEEE2003, Portland, Oct, 200

CMOS Architectures and circuits for high-speed decision-making from image flows

We present architectures, CMOS circuits and CMOS chips to process image flows at very high speed. This is achieved by exploiting bio-inspiration and performing processing tasks in parallel manner and concurrently with image acquisition. A vision system is presented which makes decisions within sub-msec range. This is very well suited for defense and security applications requiring segmentation and tracking of rapidly moving objects

On evolution of CMOS image sensors

CMOS Image Sensors have become the principal technology in majority of digital cameras. They started replacing the film and Charge Coupled Devices in the last decade with the promise of lower cost, lower power requirement, higher integration and the potential of focal plane processing. However, the principal factor behind their success has been the ability to utilise the shrinkage in CMOS technology to make smaller pixels, and thereby have more resolution without increasing the cost. With the market of image sensors exploding courtesy their inte- gration with communication and computation devices, technology developers improved the CMOS processes to have better optical performance. Nevertheless, the promises of focal plane processing as well as on-chip integration have not been fulfilled. The market is still being pushed by the desire of having higher number of pixels and better image quality, however, differentiation is being difficult for any image sensor manufacturer. In the paper, we will explore potential disruptive growth directions for CMOS Image sensors and ways to achieve the same

Tactile sensing chips with POSFET array and integrated interface electronics

This work presents the advanced version of novel POSFET (Piezoelectric Oxide Semiconductor Field Effect Transistor) devices based tactile sensing chip. The new version of the tactile sensing chip presented here comprises of a 4 x 4 array of POSFET touch sensing devices and integrated interface electronics (i.e. multiplexers, high compliance current sinks and voltage output buffers). The chip also includes four temperature diodes for the measurement of contact temperature. Various components on the chip have been characterized systematically and the overall operation of the tactile sensing system has been evaluated. With new design the POSFET devices have improved performance (i.e. linear response in the dynamic contact forces range of 0.01–3N and sensitivity (without amplification) of 102.4 mV/N), which is more than twice the performance of their previous implementations. The integrated interface electronics result in reduced interconnections which otherwise would be needed to connect the POSFET array with off-chip interface electronic circuitry. This research paves the way for CMOS (Complementary Metal Oxide Semiconductor) implementation of full on-chip tactile sensing systems based on POSFETs

Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them