Characterization and modeling of low-frequency noise in Hf-based high -kappa dielectrics for future cmos applications

The International Technology Roadmap for Semiconductors outlines the need for high-K dielectric based gate-oxide Metal Oxide Semiconductor Field Effect Transistors for sub-45 nm technology nodes. Gate oxides of hafnium seem to be the nearest and best alternative for silicon dioxide, when material, thermal and structural properties are considered. Usage of poly-Si as a gate electrode material degrades the performance of the device and hence gate stacks based on metal gate electrodes are gaining high interest. Though a substantial improvement in the performance has been achieved with these changes, reliability issues are a cause of concern. For analog and mixed-signal applications, low-frequency (I /f~ noise is a major reliability factor. Also in recent years. low frequency noise diagnostics has become a powerful tool for device performance and reliability characterization. This dissertation work demonstrates the necessity of gate stack engineering for achieving a low I/f noise performance. Changes in the material and process parameters of the devices, impact the 1/f noise behavior. The impact of 1/f noise on gate technology and processing parameters xvere identified and investigated. The thickness and the quality of the interfacial oxide, the nitridation effects of the layers, high-K oxide, bulk properties of the high-K layer. percentage of hafnium content in the high-K, post deposition anneal (PDA) treatments, effects of gate electrode material (poly-silicon. fully silicided or metal). Gate electrode processing are investigated in detail. The role of additional interfaces and bulk layers of the gate stack is understood. The dependence of low-frequency noise on high and low temperatures was also investigated. A systematic and a deeper understanding of these parameters on 1/f noise behavior are deduced which also forms the basis for improved physics-based 1/f noise modeling. The model considers the effect of the interfacial layer and also temperature, based on tunneling based thermally activated model. The simulation results of improved drain-current noise model agree well with the experimentally calculated values

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

10-kV SiC MOSFET Power Module With Reduced Common-Mode Noise and Electric Field

The advancement of silicon carbide (SiC) power devices with voltage ratings exceeding 10 kV is expected to revolutionize medium- and high-voltage systems. However, present power module packages are limiting the performance of these unique switches. The objective of this research is to push the boundaries of high-density, high-speed, 10-kV power module packaging. The proposed package addresses the well-known electromagnetic and thermal challenges, as well as the prominent electrostatic and electromagnetic interference (EMI) issues associated with high-speed, 10-kV devices. The high-speed switching and high voltage rating of these devices causes significant EMI and high electric fields. Existing power module packages are unable to address these challenges, resulting in detrimental EMI and partial discharge that limit the converter operation. This article presents the design and testing of a 10-kV SiC mosfet power module that switches at a record 250 V/ns without compromising the signal and ground integrity due to an integrated screen reduces the common-mode current by ten times. This screen connection simultaneously increases the partial discharge inception voltage by more than 50%. With the integrated cooling system, the power module prototype achieves a power density of 4 W/mm 3

MIS capacitor studies on silicon carbide single crystals

Cubic SIC metal-insulator-semiconductor (MIS) capacitors with thermally grown or chemical-vapor-deposited (CVD) insulators were characterized by capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) measurements. The purpose of these measurements was to determine the four charge densities commonly present in an MIS capacitor (oxide fixed charge, N(f); interface trap level density, D(it); oxide trapped charge, N(ot); and mobile ionic charge, N(m)) and to determine the stability of the device properties with electric-field stress and temperature. The section headings in the report include the following: Capacitance-voltage and conductance-voltage measurements; Current-voltage measurements; Deep-level transient spectroscopy; and Conclusions (Electrical characteristics of SiC MIS capacitors)

Smart Power Devices and ICs Using GaAs and Wide and Extreme Bandgap Semiconductors

We evaluate and compare the performance and potential of GaAs and of wide and extreme bandgap semiconductors (SiC, GaN, Ga2O3, diamond), relative to silicon, for power electronics applications. We examine their device structures and associated materials/process technologies and selectively review the recent experimental demonstrations of high voltage power devices and IC structures of these semiconductors. We discuss the technical obstacles that still need to be addressed and overcome before large-scale commercialization commences

Irradiation impact on optimized 4H-SiC MOSFETs

Silicon (Si) power device’ technologies have reached a high maturity level, but current limitations on mechanic, temperature operation and electric performances require to investigate other semiconductor materials that can potentially compete with and overcome those border issues. This is the case of Silicon Carbide (SiC) and Gallium Nitride (GaN) which are becoming serious competitors to the Si due to their superior physical properties. Concerning SiC, the 4Hpolytype seems to be the best suitable candidate for high power MOSFETs according to its band gap, electric field strength, electron bulk mobility, and attainable threshold voltage, among others. But still, technological processes must be optimized in order to SiC MOSFETS can compete with their Si counterparts. This is the case of the gate oxidation process. A reduction of interface charge density is required for threshold voltage stability, and further improvements of the interface quality are also needed for high inversion mobility values. Once solved these problems, a path toward new perspectives of high power applications will be opened. This work is the direct continuation of the Aurore Constant’s work. It is focused on 4HSiC based devices, more specifically on the gate oxidation processes and their behaviour under different harsh environments. Up to now, most of the works carried out were focused on the improvement of the Silicon Dioxide-Silicon Carbide (SiO2/SiC) interface quality. Solving those problems would allow designing high-speed and low-switching losses MOSFETs. In the past work, the main strength was focused on a new surface pre-treatment and on a gate oxidation process. Results showed improved electrical performances. However, we are convinced that better values can be obtained by optimizing the post-oxidation annealing step, by performing surface counter doping or by performing special irradiation treatments. All the efforts of this work will oriented to the development of reliable SiC MOSFETs with improved electrical parameters, which can operate under harsh environments (like high temperature or proton/electron irradiated environment). Thus, the mains guidelines of this Ph. D. Thesis are in accordance with the following lines: 1. State of the art on various SiC related fields. 2. Electrical characterization processes. 3. Proton irradiation impact on 4H-SiC MOSFETs and charge build-up mechanisms theory at the SiO2/SiC interface. 4. Electron irradiation impact on 4H-SiC MOSFETs. 5. Gate oxidation and implantation processes optimization. 6. Robustness limit of the improved processes under irradiation environments.Las tecnologías de dispositivos de potencia en silicio (Si) han alcanzado una gran madurez. Sin embargo, las limitaciones del Si debidas a sus restricciones mecánicas, térmicas y eléctricas hacen necesario otros materiales semiconductores que puedan competir con el Si y superar sus limitaciones. Este es el caso del Carburo de Silicio (SiC) y del Nitruro de Galio (GaN) que ya comienzan a ser serios competidores del Si debido a sus mejores propiedades físicas. En lo que respecta al SiC, el politipo 4H es el candidato más adecuado para la integración de MOSFETs de potencia debido, entre otros, a los valores del bandgap, campo eléctrico crítico, movilidad volumíca de los electrones y tensión umbral alcanzable. A pesar de estas ventajas teóricas del material, es necesario optimizar cada uno de los procesos tecnológicos involucrados en la fabricación de un MOSFET en SiC para que realmente pueda competir con su contrapartida en Si. Este es el caso del proceso de oxidación para la formación del dieléctrico de puerta. Concretamente, una buena estabilidad de la tensión umbral del componente requiere disminuir la densidad de cargas en la interfase óxido/semiconductor, y mejoras adicionales en la calidad de esta interfase son también necesarias para obtener altos valores de la movilidad de los portadores en el canal de inversión. La solución de los problemas tecnológicos anteriormente enunciados abrirá nuevas perspectivas a las aplicaciones de alta potencia. Este trabajo es una continuación directa del de Aurore Constant. Se centra en dispositivos basados en 4H-SiC, y más específicamente en los procesos de oxidación de puerta, y de sus comportamientos eléctricos en diferente ambientes de trabajo hostiles. Hasta la fecha, la mayor parte de la investigación se ha centrado en la mejora de la calidad de la interfase dióxido de silicio/carburo de silicio (SiO2/SiC). La solución de estos problemas debería permitir el diseño de MOSFETs muy rápidos y con pérdidas de conmutación muy bajas. El objetivo del trabajo previo de Aurore Constant fue encontrar un nuevo procedimiento de limpieza de la superficie antes de realizar la oxidación, y en definir un nuevo proceso de oxidación para la formación del dieléctrico de puerta. Los resultados obtenidos mostraron claras mejoras del comportamiento eléctrico de los componentes. Sin embargo, estamos convencidos que la mejora podría ser aún mayor optimizando la etapa del recocido post-oxidación, utilizando un proceso adicional de dopaje superficial, o realizando un adecuado proceso de irradiación. Todos los esfuerzos de este trabajo se han dirigido al desarrollo de MOSFETs en SiC fiables, con mejores características eléctricas, y capaces de trabajar en ambientes de alta temperatura y de irradiación protónica o electrónica. En resumen, las principales líneas de esta Tesis son las siguientes: 1. Estado del arte de los diferentes dominios de trabajo del SiC. 2. Procesos y técnicas de caracterización eléctrica. 3. Impacto de la irradiación de protones en MOSFETs fabricados en 4H-SiC, y descripción teórica de los mecanismos de creación de carga en la interfase SiO2/SiC. 4. Impacto de la irradiación electrónica en MOSFETs fabricados en 4H-SiC. 5. Optimización de los procesos de oxidación y de implantación. 6. Límite de robustez de los procesos tecnológicos optimizados en ámbitos irradiados.Postprint (published version